VST(5)						      VHDL subset of ASIM/LIP6/CAO-VLSI lab.						    VST(5)

NAME

       vst
       VHDL structural subset.

ORIGIN

       This  software  belongs	to  the  ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in
       Paris, France.

       Web : http://asim.lip6.fr/recherche/alliance/
       E-mail : alliance-users@asim.lip6.fr

DESCRIPTION

       This document describes the ALLIANCE VHDL subset for structural descriptions.

       The declaration part of a structural description includes signal decalarations and component declarations.

       An internal signal can be declared of any type supported by the present VHDL subset except reg_bit and reg_vector.

       A component must be declared with exactly the same port description as in its entity specification. This means that local ports are  to	be
       declared with the same name, type and kind and in the same order.

       A  structural description is a set of component instanciation statements.  Instances' ports are connected to each other trough signals in a
       port map specification. Both explicit and implicit port map specifications are supported by the ALLIANCE VHDL subset.

       The present version of the VHDL compiler does not allow unconnected ports (the open mode is not supported).

       Only the concatenation operator (&) can be used in the actual part (effective signal conntected to a formal port) of a port map	specifica-
       tion.

EXAMPLES

       Here is the description of an adder with an accumulator register.

       entity add_accu is
       port (
	 clk	  : in	bit;
	 command  : in	bit;
	 data_in  : in	bit_vector (31 downto 0);
	 data_out : out bit_vector (31 downto 0);
	 cry_out  : out bit;
	 vdd	  : in	bit;
	 vss	  : in	bit
	 );
       end add_accu;

       architecture structural of add_accu is

       signal eff_data	: bit_vector (31 downto 0);	 -- effective operande
       signal adder_out : bit_vector (31 downto 0);	 -- adder's result
       signal accu_out	: bit_vector (31 downto 0);	 -- accumulator

       component adder
       port (a	 : in  bit_vector (31 downto 0);
	     b	 : in  bit_vector (31 downto 0);
	     res : out bit_vector (31 downto 0));
       end component;

       component and_32
       port (a	 : in  bit_vector (31 downto 0);
	     cmd : in  bit;
	     res : out bit_vector (31 downto 0));
       end component;

       component falling_edge_reg
       port (din  : in	bit_vector (31 downto 0);
	     clk  : in	bit;
	     dout : out bit_vector (31 downto 0));
       end component;

       begin

	 my_adder : adder
	 port map (a => eff_data, b => accu_out, res => adder_out);

	 my_mux   : and_32
	 port map (cmd => command, a => accu_out, res => eff_data);

	 my_reg   : falling_edge_reg
	 port map (din => adder_out, clk => clk, dout => accu_out);

       end;

SEE ALSO

       vhdl(5), vbe(5), asimut(1)

BUG REPORT

       This tool is under development at the ASIM department of the LIP6 laboratory.
       We need your feedback to improve documentation and tools.

ASIM
/LIP6							  October 1, 1997							    VST(5)