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fnf(1) fnf(1)

NAME
fnf - translate from FNF format to other formats

SYNOPSIS
fnf [options]

DESCRIPTION
FNF (Free Netlist Format) is an elaborated, hierarchical, register transfer level (RTL) netlist format used to communicate design informa-
tion between frontend EDA tools.

The FNF tool translates an FNF netlist to Verilog, VHDL, C, and NuSMV.

OPTIONS
Options are processed in the order they are received.

-h OR -help Prints this information then exits.

-read_fnf file Read in an FNF netlist.

-write_fnf file Write out an FNF netlist.

-write_nusmv file Write out an NuSMV description.

-write_verilog file Write out a Verilog netlist.

-write_vhdl file Write out a VHDL netlist.

-write_c file

Write out a C model.
Appends '.c' and '.h' to file name.

-write_jhdl class

Write out a JHDL netlist.
Appends .java to class name.

EXAMPLES
Building an FNF netlist from Verilog using Icarus:

$ iverilog -Wall -t fnf -o my_netlist.fnf my_verilog.v

Use FNF to produce a Verilog and C model:

$ fnf -read_fnf my_netlist.fnf -write_verilog my_netlist.v -write_c my_netlist

Use FNF to produce an NuSMV model:

$ fnf -read_fnf my_netlist.fnf -write_nusmv my_netlist.smv

Use FNF to produce another FNF netlist:

$ fnf -read_fnf my_netlist.fnf -write_fnf my_netlist2.fnf

KNOWN LIMITATIONS
General

o No tristate support.

o No memory support.

o No division or modulo operators.

Icarus Verilog FNF Code Generator

o Assumes ports and named signals have [n:0] ordering.

o "always" blocks are constrained to the Icarus Verilog synthesizable subset.

o All register clocks and asynchronous resets must be senitive on the rising edge. WARNING: No errors will be issued if a design
contains "negedge".

o All arithmetic operations must be unsigned. WARNING: No errors will be issued if a design contains signed operations.

o Multipliers can not be embbeded in concatenations.

Verilog and VHDL Model Writer

o Netlist is flat.

NuSMV Model Writer

- 2-value model.
No X's or Z's.

o Inputs assumed to init to 0.

o Registers are initialized to 0.

VERSION
0.10.6

AUTHOR
Tom Hawkins

SEE ALSO
FNF and Confluence : http://www.confluent.org/

Icarus Verilog
: http://www.icarus.com/eda/verilog/

NuSMV : http://nusmv.irst.itc.it/

31 January 2010 fnf(1)

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Netlist::Pin(3pm)					User Contributed Perl Documentation					 Netlist::Pin(3pm)

NAME

       Verilog::Netlist::Pin - Pin on a Verilog Cell

SYNOPSIS

	 use Verilog::Netlist;

	 ...
	 my $pin = $cell->find_pin ('pinname');
	 print $pin->name;

DESCRIPTION

       A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell.  A Pin connects a net in the
       current design to a port on the instantiated cell's module.

ACCESSORS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->cell
	   Reference to the Verilog::Netlist::Cell the pin is under.

       $self->comment
	   Returns any comments following the definition.  keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

       $self->delete
	   Delete the pin from the cell it's under.

       $self->module
	   Reference to the Verilog::Netlist::Module the pin is in.

       $self->name
	   The name of the pin.  May have extra characters to make vectors connect, generally portname is a more readable version.  There may be
	   multiple pins with the same portname, only one pin has a given name.

       $self->net
	   Reference to the Verilog::Netlist::Net the pin connects to.	Only valid after a link.

       $self->netlist
	   Reference to the Verilog::Netlist the pin is in.

       $self->netname
	   The net name the pin connects to.

       $self->portname
	   The name of the port connected to.

       $self->port
	   Reference to the Verilog::Netlist::Port the pin connects to.  Only valid after a link.

MEMBER FUNCTIONS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->lint
	   Checks the pin for errors.  Normally called by Verilog::Netlist::lint.

       $self->dump
	   Prints debugging information for this pin.

DISTRIBUTION

       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite.  The latest version is available from CPAN and
       from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2012 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either
       the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

perl v5.14.2							    2012-05-04							 Netlist::Pin(3pm)

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