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Special Forums UNIX and Linux Applications High Performance Computing Memory Barriers for (Ubuntu) Linux (i686) Post 302430438 by Corona688 on Thursday 17th of June 2010 03:00:49 PM
Old 06-17-2010
Small world, how so? Smilie
Quote:
Originally Posted by gorga
I hadn't heard of futexes until you mentioned them, but I did some reading and it seems they still use atomic instructions to update shared variables.
Well, yes. It has to synchronize somehow. One way or another you must interrupt other cores with this change in status, or they may never know.
Quote:
In that case I could just use one of GCC's built-in atomic operations like "__sync_fetch_ and_ add" or "__sync_bool_compare_and_swap" as described here...

Atomic Builtins - Using the GNU Compiler Collection (GCC)
Wow, those are nice.

Quote:
The thing with these is they use the asm op-code "lock", which issues a hardware lock on the data-bus effectively locking every other process out of memory.
I think you're overreacting... Any memory I/O monopolizes the bus*, LOCK just guarantees one instruction gets two ops in a row.

Also. The original 8088 has precisely one instruction worth of cache, so locking the bus stalls it instantly... The huge caches, multiple independent memory buses, and cache communication systems in recent NUMA systems usually let cores keep going or find something else to do. I'm not sure LOCK XCGH even forces a real memory fetch anymore(might be simple to test, try to get back to you on that.)

Lastly, if you're doing no mutexing, what are you doing instead -- polling? That's not going to be more efficient, untold amounts of CPU will be expended on what amounts to a while(1) loop.

I really think pthreads is still what you're looking for. They've made it as fast as they know how, significantly changing the kernel to accommodate it.

* Exceptions exist for very special-purpose memory chips like video RAM.
 

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membar_ops(9F)															    membar_ops(9F)

NAME
membar_ops, membar_enter, membar_exit, membar_producer, membar_consumer - memory access synchronization barrier operations SYNOPSIS
#include <sys/atomic.h> void membar_enter(void); void membar_exit(void); void membar_producer(void); void membar_consumer(void); The membar_enter() function is a generic memory barrier used during lock entry. It is placed after the memory operation that acquires the lock to guarantee that the lock protects its data. No stores from after the memory barrier will reach visibility and no loads from after the barrier will be resolved before the lock acquisition reaches global visibility. The membar_exit() function is a generic memory barrier used during lock exit. It is placed before the memory operation that releases the lock to guarantee that the lock protects its data. All loads and stores issued before the barrier will be resolved before the sub- sequent lock update reaches visibility. The membar_enter() and membar_exit() functions are used together to allow regions of code to be in relaxed store order and then ensure that the load or store order is maintained at a higher level. They are useful in the implementation of mutex exclusion locks. The membar_producer() function arranges for all stores issued before this point in the code to reach global visibility before any stores that follow. This is useful in producer modules that update a data item, then set a flag that it is available. The memory barrier guaran- tees that the available flag is not visible earlier than the updated data, thereby imposing store ordering. The membar_consumer() function arranges for all loads issued before this point in the code to be completed before any subsequent loads. This is useful in consumer modules that check if data is available and read the data. The memory barrier guarantees that the data is not sampled until after the available flag has been seen, thereby imposing load ordering. No values are returned. No errors are defined. These functions can be called from user or interrupt context. See attributes(5) for descriptions of the following attributes: +-----------------------------+-----------------------------+ | ATTRIBUTE TYPE | ATTRIBUTE VALUE | +-----------------------------+-----------------------------+ |Interface Stability |Evolving | +-----------------------------+-----------------------------+ atomic_add(9F), atomic_and(9F), atomic_bits(9F), atomic_cas(9F), atomic_dec(9F), atomic_inc(9F), atomic_ops(9F), atomic_or(9F), atomic_swap(9F), attributes(5), atomic_ops(3C) Atomic instructions (see atomic_ops(9F)) ensure global visibility of atomically-modified variables on completion. In a relaxed store order system, this does not guarantee that the visibility of other variables will be synchronized with the completion of the atomic instruction. If such synchronization is required, memory barrier instructions must be used. 28 Mar 2005 membar_ops(9F)
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