UNIX for Dummies Questions & Answers

I want to build a Makefile that simply takes a template file and modifies it (sed or perl, probably) before installing the result in the right place - my problem is creating the variable for substitution...

So I have

SYSTEM = SYS1 SYS2

SYS1_CHANNELS = CHANNEL1 CHANNEL2 CHANNEL4
SYS2_CHANNELS = CHANNEL3 CHANNEL5

SYS1_FTP_HOST = server1
SYS2_FTP_HOST = server2


I want to build a rule that loops through the $(SYSTEM) values and substitutes in the CHANNELS and FTP_HOST values before modding the template.

I already have...
for system in $(SYSTEM) ;\
do \
ftp_host="$$system"_FTP_HOST ;\
done;

ftp_host is correctly created (SYS1_FTP_HOST) but how do I then use the macro value associated with ftp_host ie 'server1'. It'll get more complicated still looping through the CHANNELS!

Any ideas appreciated.

I don't think you can mix shell and make like that. You can use Make's own constructs for referring to Make's own variables, but by the time the shell actually parses and executes the for loop, things are handled by the shell, and there's no way for that to refer back to Make's internal variables.

Some makes will allow you to export variables to the shell, but this is still going to be rather hard to read, understand, and debug.

Or, you could invoke Make recursively with yet more variables assigned to tell Make which actual variables to use on this invocation. Still more complexity.

Code:

target:
	for system in $(SYSTEM); do $(MAKE) SYS=$$system subtarget; done
subtarget:
	ftp_host=$($(SYS)_FTP_HOST); ... etc

For GNU Make, I could suggest some alternate approaches, but for standard make, I'd just break down and code the whole thing as a shell script, or copy+paste for each SYSTEM.

PS. Please use code tags for legibility.