Solaris

Hi all,
I'm freshman in this forum. I'm here to ask for your help. A case about Sun Fire V490. But, before starting to ask, I want to tell you the story.

Last week, I was told about a failed V490 in Da Nang City (Vietnam). It could NOT boot. After diagnosing it remotely, I found that the problem may be on the Centerplane Board. So, I took a Centerplane from a running V490 in Ho Chi Minh City and flied to Da Nang City. After replacing the centerplane, the V490 in Da Nang showed the errors :

1:0>ERROR: TEST = Run POST from Memory
1:0>H/W under test = CPU1, All CPU1 Memory
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = Incorrect checksum detected!!
Expected: ae51
Observed: 119
1:0>END_ERROR

It was NOT the errors before centerplane replacing.
OK. I called to Ha Noi City and they sent me another V490 the following day. I took the Centerplane from it and put it in the V490 in Da Nang. Problem was solved !

So, obviously, the centerplane caused the errors. But, it was abnormal when I take my Centerplane back to Ho Chi Minh City, put it in the V490 in my site, it showed exactly the errors I saw in Da Nang :

1:0>ERROR: TEST = Run POST from Memory
1:0>H/W under test = CPU1, All CPU1 Memory
1:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
1:0>MSG = Incorrect checksum detected!!
Expected: ae51
Observed: 119
1:0>END_ERROR

I don't know why and how this errors could occur ! Please advice !

Thank you very much !

How did you confirm its a centreplane? Did you perform an isolation to it?Did you see other relevant errors from the OS?

is cpu/memory different between centerplanes?

also, you should be swapping out the new nvram chip with the old one.

The V490 in Da Nang was NOT able to see the two internal FC disks. So I thought that the problem may be on the disk backplane or the data cable from the disk backplane to the centerplane or the diskbackplane power cable or the centerplane. I replaced everything of those but the centerplane, the errors were NOT changed. But when I replaced the centerplane (with the one from HCM City - my site), the errors were what you see in the previous post. And with the centerplane from HN City, everything's OK.

Those errors came from the POST level. I can't reach the ok prompt nor the OS.

Yes, there are differences. The V490 from Da Nang and Hanoi are exactly the same, with two CPU/memory boards; two 1,35 GHZ CPUs and 4 GB of RAM per board. The V490 from HCM has one CPU/memory board with two 1,5 GHZ CPU and 8 GB of RAM. The OPB version of the HCM's V490 is lower than HN's and DN's.

I don't think the NVRAM caused the errors. It's located on the I/O board, not the centerplane. Just remember, the V490 was running smoothly before i took the centerplane out for testing in Da Nang.

Thank you for you kindly support.

Here's the full log :

Hardware Power On

Probing core system FRUs.. Done
Executing POST w/%o0 = 0000.0800.0101.2041
0:0>
0:0>@(#) Sun Fire[TM] V480/V490 POST 4.18.11 2006/05/03 07:52
/export/delivery/delivery/4.18/4.18.11/post4.18.0/Camelot/cstone/integrated (root)
0:0>Copyright © 2006 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0:0>Jump from OBP->POST.
0:0>Diag level set to MIN.
0:0>Verbosity level set to NORMAL.
0:0>
0:0>Start selftest...
0:0>CPUs present in system: 0:0 2:0
0:0>Test CPU(s)..... \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ Done
0:0>Init Scan/I2C..... | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ Done
0:0>Basic Memory Test..... | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | /
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = Incorrect checksum detected!!
Expected: ae51
Observed: 119
0:0>END_ERROR

- \ | /
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = Incorrect checksum detected!!
Expected: ae51
Observed: 119
0:0>END_ERROR

-
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG =
*** Test Failed!! ***

0:0>END_ERROR

0:0>
0:0>ERROR: TEST = Run POST from Memory
0:0>H/W under test = CPU0, All CPU0 Memory
0:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0:0>MSG = ERROR: Memory error on master CPU, rolling over to new master.
0:0>END_ERROR
ü\
2:0>Start selftest...
2:0>CPUs present in system: 0:0 2:0
2:0>Test CPU(s)..... | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | Done
2:0>Init Scan/I2C..... / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | Done
2:0>Basic Memory Test..... / -
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = No Memory Detected
2:0>END_ERROR

\
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG =
*** Test Failed!! ***

2:0>END_ERROR

2:0>
2:0>ERROR: TEST = Probe and Setup Memory
2:0>H/W under test = CPU2, All CPU2 Memory
2:0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
2:0>MSG = ERROR: Memory error on master CPU, rolling over to new master.
2:0>END_ERROR

|
0:0>Start selftest...
0:0>CPUs present in system: 0:0 2:0
0:0>Test CPU(s)..... / - \ | / - \ | / - \ | / - \ | / - \ | / -

i'm trying to remember but i feel as if the obp may need to be upgraded because of the cpu difference. are the obp levels the same on both boxes (if you can remember).

i was saying to swap the new nvram with the old nvram so that you keep your old settings.

No, i think you might have misunderstood the situation. The V490 in HCMC ran fine. But I took it centerplane away, and when i put it back, it does NOT run anymore. There's no change in the system.

Is it possible that the centerplane was wrecked in transporting ? Or when i plugged it in the V490 with different CPU/Memory board, it was dumped ?

I'd thought of upgrading OBP. But how can I do it, while I can't pass the POST level ?