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Passing variable to child instance of make


 
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Old 06-07-2011
Passing variable to child instance of make

hi,
I am trying to export a variable from the parent makefile to a child instance of my makefile within the same directory.

the relevant code in my parent makefile is:
Code:
libvar := $(notdir $(basename ../src/file1))
export libvar

.PHONY: library

library:
make -f makechild libvar=file1

in the child makefile, i.e. makechild, I have the following relevant code:
LVAR: =
fname := $(addprefix lib, $(LVAR))

but obviously I am missing something because echo $(fname) returns 'lib' (instead of libfile1)when I run the make command in the parent makefile.Smilie

can you pls. help me fix the code so I can export the value of libvar into LVAR

---------- Post updated at 11:10 PM ---------- Previous update was at 09:52 PM ----------

I just figured out I was making a dumb error,
I should keep the variable names the same in both the parent and child makefile.
so, in my child makefile, I renamed LVAR to libvar and it worked.
.....just in case anyone might be interested.

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gccmakedep(1)						      General Commands Manual						     gccmakedep(1)

NAME
gccmakedep - create dependencies in makefiles using 'gcc -M' SYNOPSIS
gccmakedep [ -sseparator ] [ -fmakefile ] [ -a ] [ -- options -- ] sourcefile ... DESCRIPTION
The gccmakedep program calls 'gcc -M' to output makefile rules describing the dependencies of each sourcefile, so that make(1) knows which object files must be recompiled when a dependency has changed. By default, gccmakedep places its output in the file named makefile if it exists, otherwise Makefile. An alternate makefile may be speci- fied with the -f option. It first searches the makefile for a line beginning with # DO NOT DELETE or one provided with the -s option, as a delimiter for the dependency output. If it finds it, it will delete everything following this up to the end of the makefile and put the output after this line. If it doesn't find it, the program will append the string to the makefile and place the output after that. EXAMPLE
Normally, gccmakedep will be used in a makefile target so that typing 'make depend' will bring the dependencies up to date for the make- file. For example, SRCS = file1.c file2.c ... CFLAGS = -O -DHACK -I../foobar -xyz depend: gccmakedep -- $(CFLAGS) -- $(SRCS) OPTIONS
The program will ignore any option that it does not understand, so you may use the same arguments that you would for gcc(1), including -D and -U options to define and undefine symbols and -I to set the include path. -a Append the dependencies to the file instead of replacing existing dependencies. -fmakefile Filename. This allows you to specify an alternate makefile in which gccmakedep can place its output. Specifying "-" as the file name (that is, -f-) sends the output to standard output instead of modifying an existing file. -sstring Starting string delimiter. This option permits you to specify a different string for gccmakedep to look for in the makefile. The default is "# DO NOT DELETE". -- options -- If gccmakedep encounters a double hyphen (--) in the argument list, then any unrecognized arguments following it will be silently ignored. A second double hyphen terminates this special treatment. In this way, gccmakedep can be made to safely ignore esoteric compiler arguments that might normally be found in a CFLAGS make macro (see the EXAMPLE section above). -D, -I, and -U options appearing between the pair of double hyphens are still processed normally. SEE ALSO
gcc(1), make(1), makedepend(1). AUTHOR
gccmakedep was written by the XFree86 Project based on code supplied by Hongjiu Lu. Colin Watson wrote this manual page, originally for the Debian Project, based partly on the manual page for makedepend(1). XFree86 Version 4.7.0 gccmakedep(1)

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