Visit Our UNIX and Linux User Community


Makefile rule being skipped


 
Thread Tools Search this Thread
Top Forums Shell Programming and Scripting Makefile rule being skipped
# 1  
Old 10-13-2009
Makefile rule being skipped

I can't seem to get a rule in my Makefile to ever run... even if I change the rule to force make to re-enter the rule, or if I change the dependent files the rule depends on. Any ideas why the second rule is being ignored here?

Code:
#MAKEFILES = $(DIRS:%=$(ROOT)/%/Makefile)

#$(MAKEFILES):
#	@echo -e $(COLOR_GREEN) Making framework library: $@ $(COLOR_DEFAULT)
#	\make -f $@ build
#	@echo -e $(COLOR_GREEN) Making framework library: $@ $(COLOR_DEFAULT)
#	ar $(ARCHIVEROPTS) $@ $(OBJECTS)
#	@echo -e $(COLOR_MAGENTA) Adding objects to $(ARCHIVE) $(COLOR_DEFAULT)
#	ar $(ARCHIVEROPTS) $(ARCHIVE) $(OBJECTS)

$(ROOT)/libcommon/Makefile:
	@echo -e $(COLOR_GREEN) Making library: $@ $(COLOR_DEFAULT)
	\make -f $@ build
MAIN_CPP = $($(MAIN_LIBRARY):$(ROOT)/libmain/%/bld/main.cpp)

MAIN_OBJECT = $($(MAIN_CPP):%.cpp=%.o)

$(MAIN_LIBRARY): $(MAIN_OBJECT)
	@echo -e $(COLOR_CYAN) Compiling main from library: $@ $(COLOR_DEFAULT)
	ar $(ARCHIVEROPTS) $@ $(MAIN_OBJECT)
	@echo -e $(COLOR_MAGENTA) Adding object to $(ARCHIVE) $(COLOR_DEFAULT)
	ar $(ARCHIVEROPTS) $(ARCHIVE) $(MAIN_OBJECT)

%.o: %.cpp $(MAKE_CONFIGURATION)
	@echo -e $(COLOR_BLUE) Compiling: $@ $(COLOR_DEFAULT)
	g++ $(CPPOPTS) -frandom-seed="$(shell pwd)/$@" $(INCLUDE_DIRS:%=-I%) $< -c -o $@

BIN_DEPENDENCIES = Makefile \
				$(INCLUDE_DIRS) \
				$(LIBRARIES) \
				$(MAIN_LIBRARY) \
				$(OBJECTS)

$(BIN_TARGET): checkout_source $(ROOT)/libcommon/Makefile.portal $(MAIN_LIBRARY) $(OBJECTS)
	@echo -e $(_COLOR_CYAN)Linking: $@ $(_COLOR_DEFAULT)
	@echo -e $(_COLOR_CYAN)USING ARCHIVE $(_COLOR_DEFAULT)
	g++ $(LINKOPTS) -Wl \
	\
	$(INCLUDE_DIRS:%=-I%) \
	\
	$(ARCHIVE) \
	\
	$(BOOST_LIBRARIES:%=-l%) -o $(BIN_TARGET)

dumpvars:
	@echo G_CPPS $(G_CPPS)
	@echo G_OBJECTS $(G_OBJECTS)
	@echo INCLUDE_DIRS $(INCLUDE_DIRS)
	@echo MAKEFILES $(MAKEFILES)
	@echo MAIN_OBJECT $(MAIN_OBJECT)

The rule in bold is the rule getting skipped for some reason. I know FRAMEWORK_MAKEFILES is populated with all the proper values when I run the dumpvars rule. I commented out that rule and replaced it an exact specific rule for the makefile in a given directory rather than doing each and every rule, and it still skips the rule. I know the rule is being skipped due to the absence of the echo command.

Previous Thread | Next Thread
Test Your Knowledge in Computers #559
Difficulty: Easy
A runtime error is an error that occurs while a program is being executed.
True or False?

10 More Discussions You Might Find Interesting

1. Shell Programming and Scripting

Default rule to be executed in makefile

Hi all, I want to know the entry point (default rule to be executed) in a makefile once all defined variables are evaluated. I do not have all: in my makefile and I give "make" without any parameter in command line. thanks........ (3 Replies)
Discussion started by: useless79
3 Replies

2. Programming

Makefile No rule to make target

I am trying to create a makefile to build a program and am getting the following error: make -f tsimplex.mk make: *** No rule to make target `/main/tsimplex_main.cpp', needed by `tsimplex_main.o'. Stop. OPSYS = $(shell uname -s ) TARGET = tsimplex ROOTDIR = ../../.. GTSDIR =... (1 Reply)
Discussion started by: kristinu
1 Replies

3. Shell Programming and Scripting

Skipped duplicated files from log

I have a script to get files from remote server to local path the issue I wanna log the output of every collected files but look like something went wrong , I feel that my error is hide in what follows: In ftp function I did not manage to control if file exist in my local directory then... (2 Replies)
Discussion started by: arm
2 Replies

4. Shell Programming and Scripting

Command getting skipped

Hi All, Its been a long time!!!!!! Having one problem in our live server.... we have perl code which runs every day for almost 15 to 18hrs process and it creates almost 150 to 200 sub process (arc get) sequentially. However in which randomly one or few of the process getting skipped. But... (2 Replies)
Discussion started by: Shahul
2 Replies

5. UNIX for Dummies Questions & Answers

Defining a new suffix rule in a Makefile

Hi everybody, I have a Makefile where a single suffix rule is defined: .SUFFIXES: .cpp .cpp.o: ${CXX} ${CXXFLAGS} -c -o $@ $< And I'd like to create another where an additional flag is added to compile in SMP. Right now, I have to do it like this: interface-smp.o:... (2 Replies)
Discussion started by: Zel2008
2 Replies

6. Homework & Coursework Questions

Help with Simple Multi-Level Makefile (Extremely New at Makefile)

Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted! 1. The problem statement, all variables and given/known data: Basically, the prompt is make a makefile with various sub makefiles in their respective subdirectories. All code... (1 Reply)
Discussion started by: Tatl
1 Replies

7. UNIX for Advanced & Expert Users

Makefile executing another Makefile first?

I have 2 libraries in 2 different directories that I build with Makefiles. library B depends on library A. If I modify a .cpp file in library A and run lib B's Makefile can I have B's makefile to automatically rebuild library A? I am now rebuilding A, followed by B... but I'd like B to... (0 Replies)
Discussion started by: wwuster
0 Replies

8. Post Here to Contact Site Administrators and Moderators

Rule # 8

In light of this board's rule stating "no BSD vs. Linux vs. Windows or similar threads," is the following post legal (can I post it)? Hi. I'm thinking about obtaining a web server for business purposes and I want to learn to administer and maintain the server myself. I need to be able to use... (1 Reply)
Discussion started by: bluegospel
1 Replies

9. UNIX for Advanced & Expert Users

Makefile problem - How to run module load in a Makefile

Hi, I'm trying to run the module load command in a Makefile and i'm getting the following error: make: module: command not found Why is this? Is there any way to run this command in a Makefile? NOTE: command - module load msjava/sunjdk/1.5.0 works fine outside of the Makefile (2 Replies)
Discussion started by: hernandinho
2 Replies

10. UNIX for Dummies Questions & Answers

make and clean in a single rule in the makefile.

Hi, This stems from the following thread https://www.unix.com/showthread.php?t=18299 I have a makefile which makes either executables or a shared library. i.e. make -f unix.mak will create the executables and make -f unix.mak libolsv will create the shared library. Since these have to be... (4 Replies)
Discussion started by: vino
4 Replies

Featured Tech Videos