Makefile not work. Why?

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Makefile not work. Why?

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02-20-2008

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Makefile not work. Why?

Code:

[root@zet c1(0)]# ls
c1.0.cc  info  makefile  x.c
[root@zet c1(0)]# cat makefile 
CC=/usr/bin/g++
CFLAGS=-pedantic -ansi 
LFLAGS=
#NAME=c1.0
AUTHOR= Marcin

%.o: %.c
        $(CC) $(CFLAGS) -c $<

%: %.cc 
        $(CC) $(CFLAGS) $*.cc $(LFLAGS) -o $*

# to na wypadek gdyby pliki o tych nazwach istniały
.PHONY: clean info install

install:
        @echo "Not implemented"

#clean:
#       rm -f $(NAME1) $(NAME2)

info:
        @echo "$(AUTHOR)"
        @echo " GPL vRelease"
[root@zet c1(0)]# make
Not implemented
[root@zet c1(0)]#

marcintom

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02-21-2008

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check thest following
$which make
$make -f Makefile
$make install
$make hai

The first one will show you the version of the make if present
the second one will force make to read the 'Makefile'
the third one will tell make to make the target install
the fourth one will tell make to make the target hai, for which there is no rule, and hence would give an error 'no rule to make target hai'

best Regards,
Rakesh UV

uvrakesh

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02-21-2008

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Thx for replay but the problem is not in make program but in the makefile
Please read first post carefully

the lines with main problems :

Code:

%.o: %.c
    $(CC) $(CFLAGS) -c $<

%: %.cc
    echo $* 
    $(CC) $(CFLAGS) $*.cc $(LFLAGS) -o $*

marcintom

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02-21-2008

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hi,
make file are processed from line 1 and the first lines of you file are variables (ok) but then a role
and soon this role is processed it stops.

All you need is in the begining

myprg: myprg.o mymodul.o

since make KNOWS how to generate a binary from an .o and KNOWS how to generate a .o from
several sources including .c this should work.

Quote:

Originally Posted by marcintom

Code:

[root@zet c1(0)]# ls
c1.0.cc  info  makefile  x.c
[root@zet c1(0)]# cat makefile 
CC=/usr/bin/g++                                       <- iff you have more than one , else gcc/g++ alone is sufficent 
CFLAGS=-pedantic -ansi                       <- -better -Wall
LFLAGS=                                              <- i guess you want LDFLAGS, not used so remove
#NAME=c1.0
AUTHOR= Marcin

%.o: %.c
        $(CC) $(CFLAGS) -c $<                           <- Make knows this  remove

%: %.cc 
        $(CC) $(CFLAGS) $*.cc $(LFLAGS) -o $*   <- Make knows this  remove

# to na wypadek gdyby pliki o tych nazwach istniały
.PHONY: clean info install

install:                                                                <- 1. real rule it will executed make will stop here
        @echo "Not implemented"

#clean:
#       rm -f $(NAME1) $(NAME2)                <- $(RM)       

info:
        @echo "$(AUTHOR)"
        @echo " GPL vRelease"
[root@zet c1(0)]# make
Not implemented
[root@zet c1(0)]#

grumpf

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02-22-2008

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Hi Marcintom,
->i was just trying to see if those checks would help you
->the error was interesting, not seen before, thats why i was keen on the version of make
->and secondly you can call make in these ways
->make
it will try to make the first target and there is no constraints, that the target name should be in the first line(make parses not in a single strech, it has do a lot of substitution, get the values of macros, include other makefiles etc etc and at last it tries to make targets)

->make target
here it will try to make the target
->but in any of the two cases there is no chance that it would give a error like that (assuming that the lines in make have proper spaces and tabs)

->i was not able to get the same error when tried in read had machine with make 3.80
->please post the solution if have found one

Best Regards,
Rakesh Uv

uvrakesh

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02-22-2008

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Thank you guys for all advices.

I see now that my problem was in not to write the main target
If I correctly understand you.

and I run something lik this ( this work fine

)

Code:

CC= gcc
CFLAGS= -Wall -pedantic -ansi

myprog: x.o
    $(CC) $(CFLAGS) x.o -o myprog
%.o: %.c
    $(CC) $(CFLAGS) -c $<

to uvrakesh

yes "make" work fine

Code:

[root@zet c1(0)]# make -v
GNU Make 3.81
Copyright (C) 2006  Free Software Foundation, Inc.
[root@zet c1(0)]# ls
c1.0  c1.0.cc  info  makefile  makefile.tmp  myprog  x.c  x.o
[root@zet c1(0)]# rm myprog x.o 
rm: delete this file `myprog'? t
rm: delete this file `x.o'? t
[root@zet c1(0)]# ls
c1.0  c1.0.cc  info  makefile  makefile.tmp  x.c
[root@zet c1(0)]# make -f makefile.tmp 
gcc -Wall -pedantic -ansi  x.o -o myprog
[root@zet c1(0)]# ls
c1.0  c1.0.cc  info  makefile  makefile.tmp  myprog  x.c  x.o

PS
Sorry for my english

Last edited by marcintom; 02-25-2008 at 02:56 PM..

marcintom

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