Programming

So, gmake or make are tools to interpret makefile. The real c/c++ compilor is specified in makefile. for example: in my project makefile, there are such lines:
$(TAG)/%.o: %.c
$(CC) $(CFLAGS) $(DEBUG) -c $< -o $@

$(TAG)/%.o: %.C
$(CXX) $(CXXFLAGS) $(DEBUG) -c $< -o $@

$(TAG)/%.o: %.cpp
$(CXX) $(CXXFLAGS) $(DEBUG) -c $< -o $@

Please put code in code tags, leaving it outside destroys the formatting.

I'm sorry, I didn't realize you wanted a explanation of makefiles rather than what you asked for, the differences between two implimentations of make.

Those are suffix rules, describing how to make .o files from .c files.

$(CC) is a variable. You can change it to tell it to use different compilers.

yes,

CC is the c compiler
CXX is c++ compiler

gmake has some extended features like macro identification.. for instance the following macro ".cpp.o" can be understood by gmake but make doesnt..