Query: pci_set_cacheline_size
OS: suse
Section: 9
Format: Original Unix Latex Style Formatted with HTML and a Horizontal Scroll Bar
PCI_SET_CACHELINE_SI(9) Hardware Interfaces PCI_SET_CACHELINE_SI(9)NAMEpci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmedSYNOPSISint pci_set_cacheline_size(struct pci_dev * dev);ARGUMENTSdev the PCI device for which MWI is to be enabledDESCRIPTIONHelper function for pci_set_mwi. Originally copied from drivers/net/acenic.c. Copyright 1998-2001 by Jes Sorensen, <jestrained-monkey.org>.RETURNSAn appropriate -ERRNO error value on error, or zero for success.COPYRIGHTKernel Hackers Manual 2.6. July 2010 PCI_SET_CACHELINE_SI(9)
Related Man Pages |
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mtrr_add(9) - suse |
device_create_vargs(9) - centos |
device_schedule_callback_owner(9) - centos |
struct_bus_type(9) - centos |
struct_device_driver(9) - centos |
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