suse man page for pci_set_cacheline_size

Query: pci_set_cacheline_size

OS: suse

Section: 9

Format: Original Unix Latex Style Formatted with HTML and a Horizontal Scroll Bar

PCI_SET_CACHELINE_SI(9) 					Hardware Interfaces					   PCI_SET_CACHELINE_SI(9)

NAME
pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
SYNOPSIS
int pci_set_cacheline_size(struct pci_dev * dev);
ARGUMENTS
dev the PCI device for which MWI is to be enabled
DESCRIPTION
Helper function for pci_set_mwi. Originally copied from drivers/net/acenic.c. Copyright 1998-2001 by Jes Sorensen, <jestrained-monkey.org>.
RETURNS
An appropriate -ERRNO error value on error, or zero for success.
COPYRIGHT
Kernel Hackers Manual 2.6. July 2010 PCI_SET_CACHELINE_SI(9)
Related Man Pages
pci_create_slot(9) - suse
usb_set_interface(9) - suse
device_create(9) - centos
struct_bus_type(9) - centos
struct_input_polled_dev(9) - suse
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