fpc(3) Library Functions Manual fpc(3)Name
fpc, get_fpc_csr, set_fpc_csr, swapRM, swapINX - floating-point control registers
These functions are to get and set the floating-point control registers of RISC floating-point units. All of these functions take and
return their values as 32 bit integers.
The file <mips/fpu.h> contains unions for each of the control registers. Each union contains a structure that breaks out the bit fields
into the logical parts for each control register. This file also contains constants for fields of the control registers.
RISC floating-point implementations have a control and status register and an implementation revision register. The control and status
register is returned by The routine sets the control and status register and returns the old value. The implementation revision register
is read-only and is returned by the routine
The function sets only the rounding mode and returns the old rounding mode. The function sets only the sticky inexact bit and returns the
old one. The bits in the arguments and return values to and are right justified.
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GETFCR(2) System Calls Manual GETFCR(2)NAME
getfcr, setfcr, getfsr, setfsr - control floating point
void setfcr(ulong fcr)
void setfsr(ulong fsr)
/* Alef only */
void setfcr(uint fcr)
void setfsr(uint fsr)
These routines provide a fairly portable interface to control the rounding and exception characteristics of IEEE 754 floating point units.
In effect, they define a pair of pseudo-registers, the floating point control register, fcr, which affects rounding, precision, and excep-
tions, and the floating point status register, fsr, which holds the accrued exception bits. Each register has a get routine to retrieve
its value, a set routine to modify it, and macros that identify its contents.
The fcr contains bits that, when set, enable exceptions: FPINEX (enable inexact exceptions), FPOVFL (enable overflow exceptions), FPUNFL
(enable underflow exceptions), and FPZDIV (enable zero divide exceptions). Rounding is controlled by installing in fcr, under mask
FPRMASK, one of the values FPRNR (round to nearest), FPRZ (round towards zero), FPRPINF (round towards positive infinity), and FPRNINF
(round towards negative infinity). Precision is controlled by installing in fcr, under mask FPPMASK, one of the values FPPEXT (extended
precision), FPPSGL (single precision), and FPPDBL (double precision).
The fsr holds the accrued exception bits FPAINEX, FPAOVFL, FPAUNFL, and FPAZDIV, corresponding to the fsr bits without the A in the name.
Not all machines support all modes. If the corresponding mask is zero, the machine does not support the rounding or precision modes. On
some machines it is not possible to clear selective accrued exception bits; a setfsr clears them all. The exception bits defined here work
on all architectures.
The default state of the floating point unit is fixed for a given architecture but is undefined across Plan 9: the default is to provide
what the hardware does most efficiently. Use these routines if you need guaranteed behavior. Also, gradual underflow is not available on
The specification for these routines is the same in Alef, except that these functions (and only these functions) need the machine-dependent
include file /$objtype/include/alef/arch.h.
To enable overflow traps and make sure registers are rounded to double precision (for example on the MC68020, where the internal registers
are 80 bits long):
fcr = getfcr();
fcr |= FPOVFL;
fcr &= ~FPPMASK;
fcr |= FPPDBL;