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nand(4) [freebsd man page]

NAND(4) 						   BSD Kernel Interfaces Manual 						   NAND(4)

NAME
nand -- NAND Flash framework SYNOPSIS
device nand DESCRIPTION
The FreeBSD nand framework consists of a set of interfaces that aim to provide an extensible, object oriented environement for NAND con- trollers and NAND Flash memory chips from various hardware vendors, and to allow for uniform and flexible management of the NAND devices. It comprises of the following major components: o NAND Flash controller (NFC) interface. Defines methods which allow to send commands as well as send/receive data between the controller and a NAND chip. Back-end drivers for specific NAND controllers plug into this interface and implement low-level routines for a given NAND controller. This layer implements basic functionality of a NAND Flash controller. It allows to send command and address to chip, drive CS (chip select line), as well as read/write to the selected NAND chip. This layer is independent of NAND chip devices actually connected to the controller. o NAND chip interface. Provides basic operations like read page, program page, erase block. Currently three generic classes of drivers are available, which pro- vide support for the following chips: o large page o small page o ONFI-compliant This layer implements basic operations to be performed on a NAND chip, like read, program, erase, get status etc. Since these operations use specific commands (depending on the vendor), each chip has potentially its own implementation of the commands set. The framework is extensible so it is also possible to create a custom command set for a non standard chip support. o NANDbus. This layer is responsible for enumerating NAND chips in the system and establishing the hierarchy between chips and their supervising controllers. Its main purpose is detecting type of NAND chips connected to a given chip select (CS line). It also allows manages locking access to the NAND controller. NANDbus passes requests from an active chip to the chip controller. o NAND character / GEOM device. For each NAND chip found in a system a character and GEOM devices are created which allows to read / write directly to a device, as well as perform other specific operations (like via ioctl). There are two GEOM devices created for each NAND chip: o raw device o normal device Raw device allows to bypass ECC checking when reading/writing to it, while normal device always uses ECC algorithm to validate the read data. NAND character devices will be created for each NAND chip detected while probing the NAND controller. SEE ALSO
libnandfs(3), gnand(4), nandsim(4), nandfs(5), makefs(8), mount_nandfs(8), nandfs(8), nandsim(8), nandtool(8), newfs_nandfs(8), umount_nandfs(8) STANDARDS
Open NAND Flash Interface Working Group (ONFI). HISTORY
The nand framework support first appeared in FreeBSD 10.0. AUTHORS
The nand framework was designed and developed by Grzegorz Bernacki. This manual page was written by Rafal Jaworowski. BSD
March 8, 2012 BSD

Check Out this Related Man Page

IICBUS(4)						   BSD Kernel Interfaces Manual 						 IICBUS(4)

NAME
iicbus -- I2C bus system SYNOPSIS
device iicbus device iicbb device iic device ic device iicsmb DESCRIPTION
The iicbus system provides a uniform, modular and architecture-independent system for the implementation of drivers to control various I2C devices and to utilize different I2C controllers. I2C I2C is an acronym for Inter Integrated Circuit bus. The I2C bus was developed in the early 1980's by Philips semiconductors. Its purpose was to provide an easy way to connect a CPU to peripheral chips in a TV-set. The BUS physically consists of 2 active wires and a ground connection. The active wires, SDA and SCL, are both bidirectional. Where SDA is the Serial DAta line and SCL is the Serial CLock line. Every component hooked up to the bus has its own unique address whether it is a CPU, LCD driver, memory, or complex function chip. Each of these chips can act as a receiver and/or transmitter depending on its functionality. Obviously an LCD driver is only a receiver, while a memory or I/O chip can both be transmitter and receiver. Furthermore there may be one or more BUS MASTERs. The BUS MASTER is the chip issuing the commands on the BUS. In the I2C protocol specification it is stated that the IC that initiates a data transfer on the bus is considered the BUS MASTER. At that time all the others are regarded to as the BUS SLAVEs. As mentioned before, the IC bus is a Multi-MASTER BUS. This means that more than one IC capable of initiating data transfer can be connected to it. DEVICES
Some I2C device drivers are available: Devices Description iic general i/o operation ic network IP interface iicsmb I2C to SMB software bridge INTERFACES
The I2C protocol may be implemented by hardware or software. Software interfaces rely on very simple hardware, usually two lines twiddled by 2 registers. Hardware interfaces are more intelligent and receive 8-bit characters they write to the bus according to the I2C protocol. I2C interfaces may act on the bus as slave devices, allowing spontaneous bidirectional communications, thanks to the multi-master capabili- ties of the I2C protocol. Some I2C interfaces are available: Interface Description pcf Philips PCF8584 master/slave interface iicbb generic bit-banging master-only driver lpbb parallel port specific bit-banging interface bktr Brooktree848 video chipset, hardware and software master-only interface SEE ALSO
iicbb(4), lpbb(4), pcf(4) HISTORY
The iicbus manual page first appeared in FreeBSD 3.0. AUTHORS
This manual page was written by Nicolas Souchu. BSD
August 6, 1998 BSD
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