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fmi(1) [debian man page]

FSP(1)							     CAO-VLSI Reference Manual							    FSP(1)

NAME
fmi - FSM state miminization ORIGIN
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in Paris, France. Web : http://asim.lip6.fr/recherche/alliance/ E-mail : alliance-users@asim.lip6.fr SYNOPSIS
fmi [-V] input_file output_file DESCRIPTION
Made to run on FSM descriptions, fmi supports the same subset of VHDL as syf (for further informations about this subset see SYF(1) and FSM(5)). fmi uses a Reduced Ordered Binary Decision Diagrams representation and identifies equivalent states. After this step, it drives a new FSM where all equivalent states are replaced by a single state. As a restriction fmi doesn't handle don't cares (as this much more difficult). ENVIRONMENT VARIABLES
MBK_WORK_LIB gives the path of the FSM description. The default value is the current directory. MBK_CATA_LIB gives some auxiliary pathes for the FSM descriptions. The default value is the current directory. OPTIONS
-V Sets verbose mode on. Each step of the minimization is displayed on the standard output. EXAMPLE
fmi digi digi_min SEE ALSO
syf (1), fsp (1), fsm (5), xfsm (1). BUG REPORT
This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools. ASIM
/LIP6 October 1, 1997 FSP(1)

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SYF(1)                                                       CAO-VLSI Reference Manual                                                      SYF(1)

NAME
SYF - Finite State Machine synthesizer. ORIGIN
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in Paris, France. Web : http://asim.lip6.fr/recherche/alliance/ E-mail : alliance-users@asim.lip6.fr SYNOPSIS
syf -a|j|m|u|o|r [-CDEOPRSTV] input_name [output_name] DESCRIPTION
syf is a Finite State Machine synthesizer. syf allows a fast generation of VHDL Data Flow description (see vbe(5)) from a VHDL Finite State Machine description (see fsm(5)). The input FSM specification can use an internal STACK. Both MOORE and MEALEY FSMs can be synthe- sized, with output registers if desired. For a MOORE FSM, a timing-optimized implementation that emulates a ROM with microsequencer is possible. A scan-path for the state registers can also be implemented. ENVIRONMENT VARIABLES
MBK_WORK_LIB(1) indicates the path to the read/write directory for the session. OPTIONS
-a Uses "Asp" as encoding algorithm. -j Uses "Jedi" as encoding algorithm. -m Uses "Mustang" as encoding algorithm. -u Uses an encoding given by user through <input_name>.enc file. In this file, a line started by a # character is a comment. A valid line contains one state name followed by its hexadecimal code. -o Uses the one hot encoding algorithm. -r Uses distinct random numbers for state encoding. -C Checks the transition's consistency. -D With this option syf doesn't optimize unused, i.e Don't Care, codes. -E Saves the encoding result in the <output_name>.enc. This file has the same syntax as <input_name>.enc file which is used by -u option. -O With this option syf places registers on the outputs. -P Implements a scan-path for the state registers, stack registers and possibly output registers. Scan-path mechanism is directely included in states decoder. Users should use scapin(5) for a correct insertion of a scan-path in a netlist. Please check fsm(5) for information about scan-path descriptions. -R This option is only available for MOORE FSM. With this option, syf emulate s a ROM with micro-sequencer implementation : there is no combinatorial logic between the state registers and the FSM outputs. This can be mandatory for external timing constraints. See fsm(5) and grog(1) for more on ROM descriptions. -S With this option syf doesn't take into account the cost of the transitions to compute an encoding. -V Verbose mode on. Each step of the FSM synthesis is displayed on the standard output, along with some statistics. EXAMPLE
Environment variables: setenv MBK_WORK_LIB /alliance/tutorials/dlxm syf is called as follow (the dlx_ctrl.fsm is already created in /alliance/tutorials/dlxm) : syf -sE dlx_ctrl Two files will be generated, a states encoding file dlx_ctrls.enc and a VHDL data flow file /alliance/tutorials/dlxm/dlx_ctrls.vbe SEE ALSO
fsm(5), vbe(5), vhdl(5), boom(1), boog(1), loon(1), scapin(1), asimut(1), proof(1), MBK_WORK_LIB(1). BUG REPORT
This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools. ASIM
/LIP6 October 1, 1997 SYF(1)

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