struct_rs_control(9) [centos man page]

STRUCT 
RS_CONTROL(9)						    Structures						      STRUCT RS_CONTROL(9)

NAME

       struct_rs_control - rs control structure

SYNOPSIS

       struct rs_control {
	 int mm;
	 int nn;
	 uint16_t * alpha_to;
	 uint16_t * index_of;
	 uint16_t * genpoly;
	 int nroots;
	 int fcr;
	 int prim;
	 int iprim;
	 int gfpoly;
	 int (* gffunc) (int);
	 int users;
	 struct list_head list;
       };

MEMBERS

       mm
	   Bits per symbol

       nn
	   Symbols per block (= (1<<mm)-1)

       alpha_to
	   log lookup table

       index_of
	   Antilog lookup table

       genpoly
	   Generator polynomial

       nroots
	   Number of generator roots = number of parity symbols

       fcr
	   First consecutive root, index form

       prim
	   Primitive element, index form

       iprim
	   prim-th root of 1, index form

       gfpoly
	   The primitive generator polynominal

       gffunc
	   Function to generate the field, if non-canonical representation

       users
	   Users of this structure

       list
	   List entry for the rs control list

AUTHOR

       Thomas Gleixner <tglx@linutronix.de>
	   Author.

COPYRIGHT

Kernel Hackers Manual 3.10					     June 2014						      STRUCT RS_CONTROL(9)

STRUCT 
IRQ_CHIP_GENE(9) 					    Structures						   STRUCT IRQ_CHIP_GENE(9)

NAME

       struct_irq_chip_generic - Generic irq chip data structure

SYNOPSIS

       struct irq_chip_generic {
	 raw_spinlock_t lock;
	 void __iomem * reg_base;
	 unsigned int irq_base;
	 unsigned int irq_cnt;
	 u32 mask_cache;
	 u32 type_cache;
	 u32 polarity_cache;
	 u32 wake_enabled;
	 u32 wake_active;
	 unsigned int num_ct;
	 void * private;
	 struct list_head list;
	 struct irq_chip_type chip_types[0];
       };

MEMBERS

       lock
	   Lock to protect register and cache data access

       reg_base
	   Register base address (virtual)

       irq_base
	   Interrupt base nr for this chip

       irq_cnt
	   Number of interrupts handled by this chip

       mask_cache
	   Cached mask register

       type_cache
	   Cached type register

       polarity_cache
	   Cached polarity register

       wake_enabled
	   Interrupt can wakeup from suspend

       wake_active
	   Interrupt is marked as an wakeup from suspend source

       num_ct
	   Number of available irq_chip_type instances (usually 1)

       private
	   Private data for non generic chip callbacks

       list
	   List head for keeping track of instances

       chip_types[0]
	   Array of interrupt irq_chip_types

DESCRIPTION

       Note, that irq_chip_generic can have multiple irq_chip_type implementations which can be associated to a particular irq line of an
       irq_chip_generic instance. That allows to share and protect state in an irq_chip_generic instance when we need to implement different flow
       mechanisms (level/edge) for it.

AUTHORS

       Thomas Gleixner <tglx@linutronix.de>
	   Author.

       Ingo Molnar <mingo@elte.hu>
	   Author.

COPYRIGHT

Kernel Hackers Manual 3.10					     June 2014						   STRUCT IRQ_CHIP_GENE(9)