Linux and UNIX Man Pages

Linux & Unix Commands - Search Man Pages

lax(5) [centos man page]

LAX(5)							     CAO-VLSI Reference Manual							    LAX(5)

NAME
lax - Parameter file for logic synthesis ORIGIN
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in Paris, France. Web : http://asim.lip6.fr/recherche/alliance/ E-mail : alliance-users@asim.lip6.fr SYNOPSIS
filename.lax DESCRIPTION
The .lax file contains user modifiable parameters that lead to different logic synthesis. EXAMPLE
Circuit Interfce -- Entity Declaration ENTITY digia IS PORT ( clock : in BIT; -- clock jour : in BIT; -- jour reset : in BIT; -- reset vdd : in BIT; -- vdd vss : in BIT; -- vss i : in bit_vector(3 DOWNTO 0) ; -- i porte : out BIT; -- porte alarm : out BIT; -- alarm ep_0 : out BIT; -- ep_0 ep_1 : out BIT; -- ep_1 ep_2 : out BIT; -- ep_2 ep_3 : out BIT; -- ep_3 ep_4 : out BIT; -- ep_4 ep_5 : out BIT; -- ep_5 ep_a : out BIT -- ep_a ); END digia; -- Architecture Declaration ARCHITECTURE behaviour_data_flow OF digia IS SIGNAL cs : REG_VECTOR(0 TO 2) REGISTER; -- cs SIGNAL cs_ea : BIT; -- cs_ea SIGNAL ef_ea : BIT; -- ef_ea SIGNAL cs_e5 : BIT; -- cs_e5 SIGNAL ef_e5 : BIT; -- ef_e5 SIGNAL cs_e4 : BIT; -- cs_e4 SIGNAL ef_e4 : BIT; -- ef_e4 SIGNAL cs_e3 : BIT; -- cs_e3 SIGNAL ef_e3 : BIT; -- ef_e3 SIGNAL cs_e2 : BIT; -- cs_e2 SIGNAL ef_e2 : BIT; -- ef_e2 SIGNAL cs_e1 : BIT; -- cs_e1 SIGNAL ef_e1 : BIT; -- ef_e1 SIGNAL cs_e0 : BIT; -- cs_e0 SIGNAL ef_e0 : BIT; -- ef_e0 SIGNAL ef : BIT_VECTOR(0 TO 2); -- ef .Lax parameter file ## This line is a comment ## Set the Optimisation Mode (0..4) ## 0 : full area optimisation ## 2 : 50% area, 50% delay ## 4 : full delay optimisation ## Used by boog and loon #M{4} ## Set the Optimisation Level (1..5) ## 1 : poor optimisation - small computation time ## 5 : best optimisation - long computation time #L{5} ## External Input Delay (in ns) ## Those signals are taken into account to optimise ## the global delay of the circuit. ## Used by boog and loon #D{ i(3):300; i(0):100; jour:120; } ## Set the list of early outputs ## Some outputs may be critical. They can be ## optimized in delay before others regardless ## of the optimisation mode. #E{ porte; ep_3; } ## Set the list of auxiliary (intermediate) signals to keep ## This can be used to decrease the memory consuption ## when trying to reorder Bdds. Those signals wont ## be reordered. #S{ cs_ea; ef_0; ef_1; ef_e4; } ## The following parameters are used for whith glop ## (Delayed --#D--inputs are also used) ## Fanout factor : the max fanout of the ## output connector is multiplied by this factor #T{1000} ## Input Capacitance : The primary inputs of the circuit ## can have fanout values. (in fF) #F{ jour:50; } ## External Output Capacitance (in fF) ## Used by boog and loon #C{ porte:50; } ## External Input Impedance (in Ohms) ## Used by boog and loon #I{ jour:5000; } ## Buffered Input : this is a list of primary inputs whith ## the number of buffer you want to add. #B{ clock:1; } SEE ALSO
boom(1), boog(1). loon(1). BUG REPORT
This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools. ASIM
/LIP6 October 1, 1997 LAX(5)

Check Out this Related Man Page

LAX(5)							     CAO-VLSI Reference Manual							    LAX(5)

NAME
lax - Parameter file for logic synthesis ORIGIN
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Universite Pierre et Marie CURIE, in Paris, France. Web : http://asim.lip6.fr/recherche/alliance/ E-mail : alliance-users@asim.lip6.fr SYNOPSIS
filename.lax DESCRIPTION
The .lax file contains user modifiable parameters that lead to different logic synthesis. EXAMPLE
Circuit Interfce -- Entity Declaration ENTITY digia IS PORT ( clock : in BIT; -- clock jour : in BIT; -- jour reset : in BIT; -- reset vdd : in BIT; -- vdd vss : in BIT; -- vss i : in bit_vector(3 DOWNTO 0) ; -- i porte : out BIT; -- porte alarm : out BIT; -- alarm ep_0 : out BIT; -- ep_0 ep_1 : out BIT; -- ep_1 ep_2 : out BIT; -- ep_2 ep_3 : out BIT; -- ep_3 ep_4 : out BIT; -- ep_4 ep_5 : out BIT; -- ep_5 ep_a : out BIT -- ep_a ); END digia; -- Architecture Declaration ARCHITECTURE behaviour_data_flow OF digia IS SIGNAL cs : REG_VECTOR(0 TO 2) REGISTER; -- cs SIGNAL cs_ea : BIT; -- cs_ea SIGNAL ef_ea : BIT; -- ef_ea SIGNAL cs_e5 : BIT; -- cs_e5 SIGNAL ef_e5 : BIT; -- ef_e5 SIGNAL cs_e4 : BIT; -- cs_e4 SIGNAL ef_e4 : BIT; -- ef_e4 SIGNAL cs_e3 : BIT; -- cs_e3 SIGNAL ef_e3 : BIT; -- ef_e3 SIGNAL cs_e2 : BIT; -- cs_e2 SIGNAL ef_e2 : BIT; -- ef_e2 SIGNAL cs_e1 : BIT; -- cs_e1 SIGNAL ef_e1 : BIT; -- ef_e1 SIGNAL cs_e0 : BIT; -- cs_e0 SIGNAL ef_e0 : BIT; -- ef_e0 SIGNAL ef : BIT_VECTOR(0 TO 2); -- ef .Lax parameter file ## This line is a comment ## Set the Optimisation Mode (0..4) ## 0 : full area optimisation ## 2 : 50% area, 50% delay ## 4 : full delay optimisation ## Used by boog and loon #M{4} ## Set the Optimisation Level (1..5) ## 1 : poor optimisation - small computation time ## 5 : best optimisation - long computation time #L{5} ## External Input Delay (in ns) ## Those signals are taken into account to optimise ## the global delay of the circuit. ## Used by boog and loon #D{ i(3):300; i(0):100; jour:120; } ## Set the list of early outputs ## Some outputs may be critical. They can be ## optimized in delay before others regardless ## of the optimisation mode. #E{ porte; ep_3; } ## Set the list of auxiliary (intermediate) signals to keep ## This can be used to decrease the memory consuption ## when trying to reorder Bdds. Those signals wont ## be reordered. #S{ cs_ea; ef_0; ef_1; ef_e4; } ## The following parameters are used for whith glop ## (Delayed --#D--inputs are also used) ## Fanout factor : the max fanout of the ## output connector is multiplied by this factor #T{1000} ## Input Capacitance : The primary inputs of the circuit ## can have fanout values. (in fF) #F{ jour:50; } ## External Output Capacitance (in fF) ## Used by boog and loon #C{ porte:50; } ## External Input Impedance (in Ohms) ## Used by boog and loon #I{ jour:5000; } ## Buffered Input : this is a list of primary inputs whith ## the number of buffer you want to add. #B{ clock:1; } SEE ALSO
boom(1), boog(1). loon(1). BUG REPORT
This tool is under development at the ASIM department of the LIP6 laboratory. We need your feedback to improve documentation and tools. ASIM
/LIP6 October 1, 1997 LAX(5)
Man Page

Featured Tech Videos