You execute "make" with the arguments "foo" "." "make" and "$(EXE)".
The first error is from the shell, because "$(EXE)" means run command "EXE" in a subshell and put its output here. The shell thinks that the rest of the command depends on what EXE might output and therefor execute it first - as there is no "EXE, this fails.
Next, "make" is executed and takes the argument: "foo". For "foo" exists a target to make and "make" does try to make it but notices that it has already done so and in the meantime "foo" hasn't changed - so it tells you that "foo" is already up to date. Next make tries to "make .". As "." is the current directory and there is no rule in your makefile describing how to make "." "make" tells you so. Finally it tries to make "make", which would be (like ".") a perfectly valid target to make - IF it would exist in your makefile. As it doesn't, "make" tells you the same as with ".": it can't make it, because you haven't told it how.
But instead of writing a long-winded make-exegesis, i could probably tell you what you need to know, so: what exactly do you want to achieve? Have you ever used a makefile and know its purposes? Its syntax?
I am new to creating makefiles.
I have several fortran programs in a folder called as "test" and also have several subroutines in another folder (which is inside this test folder) called as libry
My makefile is in the folder "test"
I want to create a makefile which can access the files in... (2 Replies)
Hi, I'm trying to run the module load command in a Makefile and i'm getting the following error:
make: module: command not found
Why is this? Is there any way to run this command in a Makefile?
NOTE: command - module load msjava/sunjdk/1.5.0 works fine outside of the Makefile (2 Replies)
I have 2 libraries in 2 different directories that I build with Makefiles.
library B depends on library A. If I modify a .cpp file in library A and run lib B's Makefile can I have B's makefile to automatically rebuild library A?
I am now rebuilding A, followed by B... but I'd like B to... (0 Replies)
Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted!
1. The problem statement, all variables and given/known data:
Basically, the prompt is make a makefile with various sub makefiles in their respective subdirectories. All code... (1 Reply)
Use and complete the template provided. The entire template must be completed. If you don't, your post may be deleted!
1. The problem statement, all variables and given/known data:
I have been trying to make the program swap but i have been getting errors with the makefile such as
driver.o:... (1 Reply)
I'm really confused how to use a makefile.
Are you supposed to be make a file from emacs called MakeFile and put code in there to compile?
I am trying to create a makefile to compile two .cpp files in my current directory to produce two .o files and then link them...
What I did was make a... (1 Reply)
Dear all,
I have a quite simple question about how to manipulate "makefile.am". I intend to:
1. "CFLAGS" and "CXXFLAGS" have no value at all. I know that these values get "-g -O2" by default. On the other hand, when I try to set them as "CFLAGS = " in "makefile.am", I get warning messages... (4 Replies)
Hey everybody,
This may be stup*d question for you, but i am new in unix and i wonder how can i make the rules for translating and linking my .c "primjer1.c", "primjer2.c" and "primjer3.c" in makefile.
Thank you. (7 Replies)
Hi All,
We have moved our OS from Sun Solaris to Linux and also some of the compilers.
Our old makefile used to be as below:
CC=cc
FLAGS=-G -KPIC -DLG_SOLARIS_OS
DEFINES=-DSunOS
SYSLIBS=-lc
.SUFFIXES : .c
.c.o : ;$(CC) -c $(FLAGS) $(DEFINES) $*.c -o $*.o
... (3 Replies)
Discussion started by: shash
3 Replies
LEARN ABOUT V7
make
MAKE(1) General Commands Manual MAKE(1)NAME
make - maintain program groups
SYNOPSIS
make [ -f makefile ] [ option ] ... file ...
DESCRIPTION
Make executes commands in makefile to update one or more target names. Name is typically a program. If no -f option is present, `make-
file' and `Makefile' are tried in order. If makefile is `-', the standard input is taken. More than one -f option may appear
Make updates a target if it depends on prerequisite files that have been modified since the target was last modified, or if the target does
not exist.
Makefile contains a sequence of entries that specify dependencies. The first line of an entry is a blank-separated list of targets, then a
colon, then a list of prerequisite files. Text following a semicolon, and all following lines that begin with a tab, are shell commands to
be executed to update the target.
Sharp and newline surround comments.
The following makefile says that `pgm' depends on two files `a.o' and `b.o', and that they in turn depend on `.c' files and a common file
`incl'.
pgm: a.o b.o
cc a.o b.o -lm -o pgm
a.o: incl a.c
cc -c a.c
b.o: incl b.c
cc -c b.c
Makefile entries of the form
string1 = string2
are macro definitions. Subsequent appearances of $(string1) are replaced by string2. If string1 is a single character, the parentheses
are optional.
Make infers prerequisites for files for which makefile gives no construction commands. For example, a `.c' file may be inferred as prereq-
uisite for a `.o' file and be compiled to produce the `.o' file. Thus the preceding example can be done more briefly:
pgm: a.o b.o
cc a.o b.o -lm -o pgm
a.o b.o: incl
Prerequisites are inferred according to selected suffixes listed as the `prerequisites' for the special name `.SUFFIXES'; multiple lists
accumulate; an empty list clears what came before. Order is significant; the first possible name for which both a file and a rule as
described in the next paragraph exist is inferred. The default list is
.SUFFIXES: .out .o .c .e .r .f .y .l .s
The rule to create a file with suffix s2 that depends on a similarly named file with suffix s1 is specified as an entry for the `target'
s1s2. In such an entry, the special macro $* stands for the target name with suffix deleted, $@ for the full target name, $< for the com-
plete list of prerequisites, and $? for the list of prerequisites that are out of date. For example, a rule for making optimized `.o'
files from `.c' files is
.c.o: ; cc -c -O -o $@ $*.c
Certain macros are used by the default inference rules to communicate optional arguments to any resulting compilations. In particular,
`CFLAGS' is used for cc and f77(1) options, `LFLAGS' and `YFLAGS' for lex and yacc(1) options.
Command lines are executed one at a time, each by its own shell. A line is printed when it is executed unless the special target `.SILENT'
is in makefile, or the first character of the command is `@'.
Commands returning nonzero status (see intro(1)) cause make to terminate unless the special target `.IGNORE' is in makefile or the command
begins with <tab><hyphen>.
Interrupt and quit cause the target to be deleted unless the target depends on the special name `.PRECIOUS'.
Other options:
-i Equivalent to the special entry `.IGNORE:'.
-k When a command returns nonzero status, abandon work on the current entry, but continue on branches that do not depend on the current
entry.
-n Trace and print, but do not execute the commands needed to update the targets.
-t Touch, i.e. update the modified date of targets, without executing any commands.
-r Equivalent to an initial special entry `.SUFFIXES:' with no list.
-s Equivalent to the special entry `.SILENT:'.
FILES
makefile, Makefile
SEE ALSO sh(1), touch(1)
S. I. Feldman Make - A Program for Maintaining Computer Programs
BUGS
Some commands return nonzero status inappropriately. Use -i to overcome the difficulty.
Commands that are directly executed by the shell, notably cd(1), are ineffectual across newlines in make.
MAKE(1)