Top Forums UNIX for Advanced & Expert Users Solaris and Linux system information. Post 302156550 by drl on Tuesday 8th of January 2008 12:50:48 PM
Old 01-08-2008

These kinds of comparisons can be difficult. I think both hardware and software need to be considered.
the CPU on linux box is 2.80GHz and on solaris box is 900 MHz made the difference?
Not necessarily, let us look a bit more.

You are comparing a 64-bit native RISC system, the SPARCV9, to a most-likely-32-bit CISC system, the Intel Xeon. Typically, a RISC system does not need the high clock speed of CISC. Is the Xeon Linux 32-bit or 64-bit?

I have used boxes that have that Intel Xeon CPU (2.8 GHz), and the predecessor of the SPARCV9, an Ultra-2 (but with 200 MHz clock).

Did you do the preparation of the program? At one time (in the 1990s) when I was comparing machines, we would often get codes that ran on IBM 3090s, and they didn't run too quickly on a Cray-2. When we looked in detail at the code, there were lots of double precision declarations, the 3090 being 32-bit machines. The Crays were 64-bit. Once we had made the adjustment, the code almost always ran faster on the Cray.

The options chosen for compilation can make a lot of difference. Compilers that are proprietary might produce faster code than others. Are the supporting libraries the same or equivalent? Looking for the best algorithm is the best use of time when optimizing.

As porter mentioned, one aspect is IO. For IO-bound jobs, you need good disks, as well as good hardware to get the data to and from the disks. Do you have the same facilities on both boxes? The designers of the Xeon box I mentioned earlier incorporated a really fast FSB, which helps the balance of large-scale application programs -- they often do some computing, then a lot of IO, then compute, IO, etc., in cycles.

I think you are on the right track -- clock rates, all the specs, etc., are not the issue. It's how your program runs that will determine the best machine -- for this one application. However, I recommend that you spend some time making sure that the playing field is at least approximately level. If you are going to run other programs, then you will need a representative sample of those runs for a comparison. For example, the ETA-10 series were really good for vector-class problems, but not very good for scalar codes. Ask yourself: what is the mix that I will be using?

Best wishes, keep us posted ... cheers, drl

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ggGetSwarType(3)							GGI							  ggGetSwarType(3)

ggGetSwarType - Get CPU features SYNOPSIS
#include <ggi/gg.h> #if defined GG_HAVE_INT64 #endif #if defined GG_LITTLE_ENDIAN #endif #if defined GG_BIG_ENDIAN #endif gg_swartype ggGetSwarType(void); DESCRIPTION
The GG_HAVE_INT64 macro is defined on 64-bit architectures where 64-bit integer values function as normal integer values with respect to C operations. Otherwise it is not defined. The GG_LITTLE_ENDIAN or GG_BIG_ENDIAN are defined, respectively, when the architecture stores values in little or big endian order. One of the two will be defined, the other undefined, accordingly. SWAR stands for SIMD Within A Register. The most well known example of SWAR is Intel MMX technology. ggGetSwarType tells which specific SWAR instruction sets the CPU implements. This is useful to choose at runtime a machine-specific imple- mentation of a very calculation-intensive routine. SWAR detection is done once during ggInit(3) and the value is cached for future use, thus it should be fast enough to choose implementations on the fly. However, due to this, SMP machines must have identical feature sets in all processors in order to ensure accurate results (see the GG_OPTS option description below.) RETURN VALUE
ggGetSwarType returns an integer in which each bit set means that a specific SWAR instruction set is available. The integer value may be 32 bits long or 64 bits long, depending on whether LibGG was compiled for a 32-bit or 64-bit machine, as per the GG_HAVE_INT64 macro. RECOGNIZED SWARS
The following flags are defined for all architectures. All of these flags can be OR'ed and are exclusive even between architectures. Note at this stage of development some of these SIMD sets are not yet detected correctly. GG_SWAR_NONE The CPU can run a vanilla C program. (hopefully! :-) GG_SWAR_32BITC The CPU can perform 32-bit math fast enough to give an advantage over 16-bit math for software SWAR implementations. Almost all computers will have this capability today. GG_SWAR_ALTIVEC The CPU has an AltiVec matrix coprocessor (Motorola G4.) GG_SWAR_SSE The CPU supports Intel Streaming SIMD Extensions. GG_SWAR_SSE2 The CPU supports Intel Streaming SIMD Extensions Version 2. GG_SWAR_SSE3 The CPU supports Intel Streaming SIMD Extensions Version 3. GG_SWAR_MMX The CPU supports Intel Multimedia Extensions. GG_SWAR_MMXPLUS The CPU supports Cyrix enhancements to Intel Multimedia Extensions. GG_SWAR_3DNOW The CPU supports AMD 3DNOW! instructions. GG_SWAR_ADV3DNOW The CPU supports AMD Advanced 3DNOW! instructions. GG_SWAR_MAX The CPU supports PA-RISC MAX Instructions. GG_SWAR_SIGD The CPU supports Microunity Mediaprocessor SIGD instructions. Additionally, 64 bits architectures define the following flags: GG_SWAR_64BITC The CPU can perform 64-bit math fast enough to give an advantage over 32-bit and 16-bit math for software SWAR implementations. GG_SWAR_MVI The CPU supports DEC (Compaq) Alpha Motion Video Instructions. GG_SWAR_MAX2 The CPU supports PA-RISC MAX2 Instructions. GG_SWAR_MDMX The CPU supports MIPS Digital Media Extension (MaDMaX) Instructions. GG_SWAR_MAJC The CPU supports SUN Microprocessor Architecture for Java Computing. GG_SWAR_VIS The CPU supports the SUN Visual Instruction Set ENVIRONMENT VARIABLE
If the "-banswar=0xhexnumber" option is present in the GG_OPTS environment variable when ggInit is first called, bits set in the 0xhexnum- ber field will not be presented to the application in the return value of ggGetSwarType. This feature can be used for performance bench- marking, to disable the use of certain SWAR implementations. It may also be used if a multiproccesor machine mis-detects the usable SWAR instruction set because the processors are not identical. BUGS
No support is currently implemented for PDP endian machines. SWAR detection code is incomplete for many architectures, and as such LibGG may may fail to detect SWAR in the CPU. libgg-1.0.x 2005-08-26 ggGetSwarType(3)

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