|
|
|
google unix.com
|
|||||||
| Forums | Register | Forum Rules | Links | Albums | FAQ | Members List | Calendar | Search | Today's Posts | Mark Forums Read |
| SUN Solaris The Solaris Operating System, usually known simply as Solaris, is a free Unix-based operating system introduced by Sun Microsystems . |
More UNIX and Linux Forum Topics You Might Find Helpful
|
||||
| Thread | Thread Starter | Forum | Replies | Last Post |
| Problem While Configuring IPMP on Sun Fire V490 | iBot | Solaris BigAdmin RSS | 0 | 05-21-2009 12:00 AM |
| Sun Fire T 2000 Booting problem | solaris8in | SUN Solaris | 6 | 10-08-2008 01:27 PM |
| Sun Fire v440 keeps shutting down | Tibor | SUN Solaris | 1 | 02-08-2008 07:31 AM |
| hardware problem? | hshapiro | SUN Solaris | 5 | 05-21-2007 05:07 PM |
| Sun Fire V440 and Patch 109147-39 | BOFH | SUN Solaris | 2 | 11-28-2005 02:49 PM |
 |
Powered by 
|
|
|
LinkBack | Thread Tools | Search this Thread |
Rating: 
|
Display Modes |
|
|
05-30-2009
|
||||
|
||||
|
Sun Fire v440 hardware problem (can't get ok>)
First of all it's shut down 60 second after power on and write on console :
SC Alert: Correct SCC not replaced - shutting managed system down! This is cured by moving out battery from ALOM card. Now server start to loop during the testing. That's on the console: Code:
>@(#) Sun Fire[TM] V440,Netra[TM] 440 POST 4.17.2 2005/07/21 12:50
/export/delivery/delivery/4.17/4.17.2/post4.17.0/Fiesta/chalupa/integrate
d (root)
0>Copyright ╘ 2005 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0>Hard Powerup RST thru SW
0>OBP->POST Call with %o0=00001000.01ff2000.
0>Diag level set to MIN.
0>Verbosity level set to MAX.
0>I/O port set to TTYA.
0>Start Selftest.....
0>CPUs present in system: 0 1 2 3
SC Alert: Host system has shut down.
0>Test CPU(s).....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Scrub and Setup L2 Cache
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Test Mailbox
0>Scrub Mailbox
0>CPU Tick and Tick Compare Registers Test
0>CPU Stick and Stick Compare Registers Test
0>Set Timing
0> UltraSPARC[TM] IIIi, Version 2.4
1>Init CPU
2>Init CPU
3>Init CPU
1> UltraSPARC[TM] IIIi, Version 2.4
2> UltraSPARC[TM] IIIi, Version 2.4
3> UltraSPARC[TM] IIIi, Version 2.4
1>DMMU
2>DMMU
3>DMMU
1>DMMU TLB DATA RAM Access
2>DMMU TLB DATA RAM Access
3>DMMU TLB DATA RAM Access
1>DMMU TLB TAGS Access
2>DMMU TLB TAGS Access
3>DMMU TLB TAGS Access
1>IMMU Registers Access
2>IMMU Registers Access
3>IMMU Registers Access
1>IMMU TLB DATA RAM Access
2>IMMU TLB DATA RAM Access
3>IMMU TLB DATA RAM Access
1>IMMU TLB TAGS Access
2>IMMU TLB TAGS Access
3>IMMU TLB TAGS Access
1>Init mmu regs
2>Init mmu regs
3>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1> Size = 00000000.00100000...
2>Setup L2 Cache
2>L2 Cache Control = 00000000.00f04400
2> Size = 00000000.00100000...
3>Setup L2 Cache
3>L2 Cache Control = 00000000.00f04400
3> Size = 00000000.00100000...
1>Scrub and Setup L2 Cache
2>Scrub and Setup L2 Cache
3>Scrub and Setup L2 Cache
1>Setup and Enable DMMU
2>Setup and Enable DMMU
3>Setup and Enable DMMU
1>Setup DMMU Miss Handler
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
1>Test Mailbox
2>Test Mailbox
3>Test Mailbox
****** POST Running ******
****** POST Running ******
1>Scrub Mailbox
2>Scrub Mailbox
3>Scrub Mailbox
****** POST Running ******
1>CPU Tick and Tick Compare Registers Test
2>CPU Tick and Tick Compare Registers Test
3>CPU Tick and Tick Compare Registers Test
1>CPU Stick and Stick Compare Registers Test
2>CPU Stick and Stick Compare Registers Test
3>CPU Stick and Stick Compare Registers Test
1>Setup Int Handlers
2>Setup Int Handlers
3>Setup Int Handlers
0>Interrupt Crosscall.....
0>Setup Int Handlers
0>Send Int CPU 1
0>Send Int CPU 2
0>Send Int CPU 3
1>Send Int to Master CPU
2>Send Int to Master CPU
3>Send Int to Master CPU
0>MB: Part-Dash-Rev#: 5016344-07-50 Serial#: 003117
0>CPU0: Part-Dash-Rev#: 5016369-03-51 Serial#: 017409
0>CPU1: Part-Dash-Rev#: 5016369-03-51 Serial#: 017418
0>CPU2: Part-Dash-Rev#: 5016369-03-51 Serial#: 017450
0>CPU3: Part-Dash-Rev#: 5016369-03-51 Serial#: 012504
****** POST Running ******
0>Set CPU/System Speed
0>........
****** POST Running ******
0>Send MC Timing CPU 1
****** POST Running ******
0>Send MC Timing CPU 2
0>Send MC Timing CPU 3
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
2>Probe Dimms
3>Probe Dimms
1>Init Mem Controller Regs
2>Init Mem Controller Regs
3>Init Mem Controller Regs
0>Init Mem Controller Regs
1>Set JBUS config reg
2>Set JBUS config reg
3>Set JBUS config reg
0>Set JBUS config reg
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Do PLL reset
0>Setting timing to 6:1 9:1, system frequency 177 MHz, CPU frequency 1062 MHz
SC Alert: Host System has Reset
0>Soft Power-on RST thru SW
0>PLL Reset.....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
0> UltraSPARC[TM] IIIi, Version 2.4
1>Init CPU
1> UltraSPARC[TM] IIIi, Version 2.4
2>Init CPU
3>Init CPU
2> UltraSPARC[TM] IIIi, Version 2.4
3> UltraSPARC[TM] IIIi, Version 2.4
1>Init mmu regs
2>Init mmu regs
3>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1> Size = 00000000.00100000...
2>Setup L2 Cache
2>L2 Cache Control = 00000000.00f04400
2> Size = 00000000.00100000...
3>Setup L2 Cache
3>L2 Cache Control = 00000000.00f04400
3> Size = 00000000.00100000...
1>Setup and Enable DMMU
2>Setup and Enable DMMU
3>Setup and Enable DMMU
1>Setup DMMU Miss Handler
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
1>Scrub Mailbox
2>Scrub Mailbox
3>Scrub Mailbox
1>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
2>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
3>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
0>Init Memory.....
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
2>Probe Dimms
3>Probe Dimms
1>Init Mem Controller Regs
2>Init Mem Controller Regs
3>Init Mem Controller Regs
0>Init Mem Controller Regs
1>Set JBUS config reg
2>Set JBUS config reg
3>Set JBUS config reg
0>Set JBUS config reg
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Do PLL reset
0>Setting timing to 6:1 9:1, system frequency 177 MHz, CPU frequency 1062 MHz
SC Alert: Host System has Reset
0>Soft Power-on RST thru SW
0>PLL Reset.....
0>Init SB
0>Initialize I2C Controller
0>Init CPU
0>Init mmu regs
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
0>Scrub Mailbox
0>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
0> UltraSPARC[TM] IIIi, Version 2.4
1>Init CPU
1> UltraSPARC[TM] IIIi, Version 2.4
2>Init CPU
3>Init CPU
2> UltraSPARC[TM] IIIi, Version 2.4
3> UltraSPARC[TM] IIIi, Version 2.4
1>Init mmu regs
2>Init mmu regs
3>Init mmu regs
1>Setup L2 Cache
1>L2 Cache Control = 00000000.00f04400
1> Size = 00000000.00100000...
2>Setup L2 Cache
2>L2 Cache Control = 00000000.00f04400
2> Size = 00000000.00100000...
3>Setup L2 Cache
3>L2 Cache Control = 00000000.00f04400
3> Size = 00000000.00100000...
1>Setup and Enable DMMU
2>Setup and Enable DMMU
3>Setup and Enable DMMU
1>Setup DMMU Miss Handler
2>Setup DMMU Miss Handler
3>Setup DMMU Miss Handler
1>Scrub Mailbox
2>Scrub Mailbox
3>Scrub Mailbox
1>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
2>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
3>Timing is 6:1 9:1, sys 177 MHz, CPU 1062 MHz, mem 118 MHz.
0>Init Memory.....
0>Probe Dimms
1>Probe Dimms
2>Probe Dimms
3>Probe Dimms
1>Init Mem Controller Sequence
2>Init Mem Controller Sequence
3>Init Mem Controller Sequence
0>Init Mem Controller Sequence
0>IO-Bridge unit 0 init test
0>IO-Bridge unit 1 init test
0>Test Memory.....
0>Select Bank Config
0>Probe and Setup Memory
0>INFO: 1024MB Bank 0, Dimm Type X4
0>INFO: No memory detected in Bank 1
0>INFO: 1024MB Bank 2, Dimm Type X4
0>INFO: No memory detected in Bank 3
0>
0>Data Bitwalk on Master
0> Test Bank 0.
0> Test Bank 2.
0>Address Bitwalk on Master
0>Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.40000000.
0>Addr walk mem test on CPU 0 Bank 2: 00000002.00000000 to 00000002.40000000.
0>Set Mailbox
0>Final mc1 is 30000026.3e781c40.
0>Setup Final DMMU Entries
0>Post Image Region Scrub
0>Run POST from Memory
1>Waiting for master CPU=0, timeout in 134 seconds...
2>Waiting for master CPU=0, timeout in 134 seconds...
3>Waiting for master CPU=0, timeout in 134 seconds...
0>Verifying checksum on copied image.
0>The Memory's CHECKSUM value is 6df0.
0>The Memory's Content Size value is 818f9.
0>Success... Checksum on Memory Validated.
1>Select Bank Config
2>Select Bank Config
3>Select Bank Config
1>Probe and Setup Memory
1>INFO: 1024MB Bank 0, Dimm Type X4
1>INFO: No memory detected in Bank 1
1>INFO: 1024MB Bank 2, Dimm Type X4
1>INFO: No memory detected in Bank 3
1>
2>Probe and Setup Memory
2>INFO: 1024MB Bank 0, Dimm Type X4
2>INFO: No memory detected in Bank 1
2>INFO: 1024MB Bank 2, Dimm Type X4
2>INFO: No memory detected in Bank 3
2>
3>Probe and Setup Memory
3>INFO: 1024MB Bank 0, Dimm Type X4
3>INFO: No memory detected in Bank 1
3>INFO: 1024MB Bank 2, Dimm Type X4
3>INFO: No memory detected in Bank 3
3>
1>Set Mailbox
2>Set Mailbox
3>Set Mailbox
1>Final mc1 is 30000026.3e781c40.
2>Final mc1 is 30000026.3e781c40.
3>Final mc1 is 30000026.3e781c40.
0>Data Bitwalk on Slave 1
0> Test Bank 0.
0> Test Bank 2.
0>Data Bitwalk on Slave 2
0> Test Bank 0.
0> Test Bank 2.
0>Data Bitwalk on Slave 3
0> Test Bank 0.
0> Test Bank 2.
0>Address Bitwalk on Slave 1
0>Addr walk mem test on CPU 1 Bank 0: 00000010.00000000 to 00000010.40000000.
0>Addr walk mem test on CPU 1 Bank 2: 00000012.00000000 to 00000012.40000000.
0>Address Bitwalk on Slave 2
0>Addr walk mem test on CPU 2 Bank 0: 00000020.00000000 to 00000020.40000000.
0>Addr walk mem test on CPU 2 Bank 2: 00000022.00000000 to 00000022.40000000.
0>Address Bitwalk on Slave 3
0>Addr walk mem test on CPU 3 Bank 0: 00000030.00000000 to 00000030.40000000.
0>Addr walk mem test on CPU 3 Bank 2: 00000032.00000000 to 00000032.40000000.
1>Setup Final DMMU Entries
2>Setup Final DMMU Entries
3>Setup Final DMMU Entries
1>Map Slave POST to master memory
2>Map Slave POST to master memory
3>Map Slave POST to master memory
1>FPU Registers and Data Path
2>FPU Registers and Data Path
3>FPU Registers and Data Path
0>FPU Registers and Data Path
1>FPU Move Registers
2>FPU Move Registers
3>FPU Move Registers
0>FPU Move Registers
1>FSR Read/Write
2>FSR Read/Write
3>FSR Read/Write
0>FSR Read/Write
1>FPU Block Register Test
2>FPU Block Register Test
3>FPU Block Register Test
0>FPU Block Register Test
1>Scrub Memory
2>Scrub Memory
3>Scrub Memory
0>Scrub Memory
2>Quick Block Mem Test
3>Quick Block Mem Test
2>Quick Test 4194304 bytes at 00000020.00000000
3>Quick Test 4194304 bytes at 00000030.00000000
0>Quick Block Mem Test
0>Quick Test 4194304 bytes at 00000000.00600000
1>Quick Block Mem Test
1>Quick Test 4194304 bytes at 00000010.00000000
2>Quick Test 4194304 bytes at 00000022.00000000
3>Quick Test 4194304 bytes at 00000032.00000000
0>Quick Test 4194304 bytes at 00000002.00000000
2>INFO: No memory detected in Bank 1
2>INFO: 1024MB Bank 2, Dimm Type X4
2>INFO: No memory detected in Bank 3
2>
3>Probe and Setup Memory
3>INFO: 1024MB Bank 0, Dimm Type X4
3>INFO: No memory detected in Bank 1
3>INFO: 1024MB Bank 2, Dimm Type X4
3>INFO: No memory detected in Bank 3
3>
1>Set Mailbox
2>Set Mailbox
3>Set Mailbox
1>Final mc1 is 30000026.3e781c40.
2>Final mc1 is 30000026.3e781c40.
3>Final mc1 is 30000026.3e781c40.
0>Data Bitwalk on Slave 1
0> Test Bank 0.
0> Test Bank 2.
0>Data Bitwalk on Slave 2
0> Test Bank 0.
0> Test Bank 2.
0>Data Bitwalk on Slave 3
0> Test Bank 0.
0> Test Bank 2.
0>Address Bitwalk on Slave 1
0>Addr walk mem test on CPU 1 Bank 0: 00000010.00000000 to 00000010.40000000.
0>Addr walk mem test on CPU 1 Bank 2: 00000012.00000000 to 00000012.40000000.
0>Address Bitwalk on Slave 2
0>Addr walk mem test on CPU 2 Bank 0: 00000020.00000000 to 00000020.40000000.
0>Addr walk mem test on CPU 2 Bank 2: 00000022.00000000 to 00000022.40000000.
0>Address Bitwalk on Slave 3
0>Addr walk mem test on CPU 3 Bank 0: 00000030.00000000 to 00000030.40000000.
0>Addr walk mem test on CPU 3 Bank 2: 00000032.00000000 to 00000032.40000000.
1>Setup Final DMMU Entries
2>Setup Final DMMU Entries
3>Setup Final DMMU Entries
1>Map Slave POST to master memory
2>Map Slave POST to master memory
3>Map Slave POST to master memory
1>FPU Registers and Data Path
2>FPU Registers and Data Path
3>FPU Registers and Data Path
0>FPU Registers and Data Path
1>FPU Move Registers
2>FPU Move Registers
3>FPU Move Registers
0>FPU Move Registers
1>FSR Read/Write
2>FSR Read/Write
3>FSR Read/Write
0>FSR Read/Write
1>FPU Block Register Test
2>FPU Block Register Test
3>FPU Block Register Test
0>FPU Block Register Test
1>Scrub Memory
2>Scrub Memory
3>Scrub Memory
0>Scrub Memory
2>Quick Block Mem Test
3>Quick Block Mem Test
2>Quick Test 4194304 bytes at 00000020.00000000
3>Quick Test 4194304 bytes at 00000030.00000000
0>Quick Block Mem Test
0>Quick Test 4194304 bytes at 00000000.00600000
1>Quick Block Mem Test
1>Quick Test 4194304 bytes at 00000010.00000000
2>Quick Test 4194304 bytes at 00000022.00000000
3>Quick Test 4194304 bytes at 00000032.00000000
0>Quick Test 4194304 bytes at 00000002.00000000
1>Quick Test 4194304 bytes at 00000012.00000000
1>Flush Caches
2>Flush Caches
3>Flush Caches
0>Flush Caches
0>XBus SRAM
0>IO-Bridge SouthBridge Remap Devs
0>IO-Bridge Tests.....
0>JBUS quick check
0> to IO-bridge_0
0> to IO-bridge_1
0>IO-Bridge unit 0 sram test
0>IO-Bridge unit 0 reg test
0>IO-Bridge unit 0 mem test
0>IO-Bridge unit 0 PCI id test
0>IO-Bridge unit 0 interrupt test
0>IO-Bridge unit 1 sram test
0>IO-Bridge unit 1 reg test
0>IO-Bridge unit 1 mem test
0>IO-Bridge unit 1 PCI id test
0>IO-Bridge unit 1 interrupt test
0>IO-Bridge unit 0 init test
1>IO-Bridge unit 0 sram test
1>IO-Bridge unit 0 reg test
1>IO-Bridge unit 0 mem test
1>IO-Bridge unit 0 PCI id test
1>IO-Bridge unit 0 interrupt test
1>IO-Bridge unit 1 init test
1>IO-Bridge unit 1 sram test
1>IO-Bridge unit 1 reg test
1>IO-Bridge unit 1 mem test
1>IO-Bridge unit 1 PCI id test
1>IO-Bridge unit 1 interrupt test
1>IO-Bridge unit 0 init test
2>IO-Bridge unit 0 sram test
2>IO-Bridge unit 0 reg test
2>IO-Bridge unit 0 mem test
2>IO-Bridge unit 0 PCI id test
2>IO-Bridge unit 0 interrupt test
2>IO-Bridge unit 1 init test
2>IO-Bridge unit 1 sram test
2>IO-Bridge unit 1 reg test
2>IO-Bridge unit 1 mem test
2>IO-Bridge unit 1 PCI id test
2>IO-Bridge unit 1 interrupt test
2>IO-Bridge unit 0 init test
3>IO-Bridge unit 0 sram test
3>IO-Bridge unit 0 reg test
3>IO-Bridge unit 0 mem test
3>IO-Bridge unit 0 PCI id test
3>IO-Bridge unit 0 interrupt test
3>IO-Bridge unit 1 init test
3>IO-Bridge unit 1 sram test
3>IO-Bridge unit 1 reg test
3>IO-Bridge unit 1 mem test
3>IO-Bridge unit 1 PCI id test
3>IO-Bridge unit 1 interrupt test
3>Print Mem Config
1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
1>Memory interleave set to 0
1> Bank 0 1024MB : 00000010.00000000 -> 00000010.40000000.
1> Bank 2 1024MB : 00000012.00000000 -> 00000012.40000000.
2>Print Mem Config
2>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
2>Memory interleave set to 0
2> Bank 0 1024MB : 00000020.00000000 -> 00000020.40000000.
2> Bank 2 1024MB : 00000022.00000000 -> 00000022.40000000.
3>Print Mem Config
3>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
3>Memory interleave set to 0
3> Bank 0 1024MB : 00000030.00000000 -> 00000030.40000000.
3> Bank 2 1024MB : 00000032.00000000 -> 00000032.40000000.
0>Print Mem Config
0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON.
0>Memory interleave set to 0
0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000.
0> Bank 2 1024MB : 00000002.00000000 -> 00000002.40000000.
0>INFO:
0> POST Passed all devices.
0>
0>POST: Return to OBP.
SC Alert: Host System has Reset
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying
_______________
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
POST Results: Cpu 0000.0000.0000.0003
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0002
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0001
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
POST Results: Cpu 0000.0000.0000.0000
%o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.54ae %o2 = ffff.ffff.ffff.ffff
Membase: 0000.0000.0000.0000
MemSize: 0000.0000.0004.0000
Init CPU arrays Done
Init E$ tags Done
Setup TLB (small-footprint mode) Done
MMUs ON
Scrubbing Tomatillo tags... 0 1
Find dropin, Copying Done, Size 0000.0000.0000.7100
PC = 0000.07ff.f000.5f48
PC = 0000.0000.0000.6048
Find dropin, Copying Done, Size 0000.0000.0001.1770
Diagnostic console initialized
Configuring system memory & CPU(s)
RED State Exception
Error enable reg: 0000.0000.0000.0000
CPU: 0000.0000.0000.0001
TL=0000.0000.0000.0005 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0004 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4200 TnPC=0000.0000.f000.4204 TSTATE=0000.0044.1500.1500
TL=0000.0000.0000.0003 TT=0000.0000.0000.0010
TPC=0000.0000.f000.4c90 TnPC=0000.0000.f000.4c94 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0002 TT=0000.0000.0000.0064
TPC=0000.0000.b214.19e0 TnPC=0000.0000.b214.19e4 TSTATE=0000.0044.1504.1400
TL=0000.0000.0000.0001 TT=0000.0000.0000.0068
TPC=0000.0000.f000.1240 TnPC=0000.0000.f000.1244 TSTATE=0000.0044.1500.0400
Could not read diag-switch? from NVRAM!
Could not read diag-level from NVRAM!
Could not read diag-script from NVRAM!
Could not read security-mode from NVRAM!
Could not read service-mode? from NVRAM!
Could not read diag-trigger from NVRAM!
Could not read verbosity from NVRAM!
@(#)OBP 4.17.2 2005/07/21 12:29 Sun Fire V440,Netra 440
Clearing TLBs
Last some line repeat How to get ok> prompt ? What is the problem with "Error enable reg"? The google don't give me an answer! Thanks for reply Last edited by DukeNuke2; 05-30-2009 at 09:29 AM.. Reason: added code tags |
|
05-30-2009
|
|||||
|
|||||
|
Looks like you need a new NVRAM chip or else at new battery for it at least. If you have another Sun machine with the same NVRAM chip model it would be worth swapping them to prove whether what I suspect is correct or not. If the NVRAM chip in this machine is definitely faulty then it can be worth cutting open the top and attaching a watch battery in place of the internal battery if you can do a bit of hardware? Take a look at: NVRAM Battery Fix FAQ and Sun 3/80 NVRAM. The fact that your NVRAM can't be read rather than just giving an empty hostid, etc means that it is probably more faulty than just having a flat battery.
|
|
05-31-2009
|
||||
|
||||
|
Quote:
I haven't messages on console like show in "NVRAM Battery Fix FAQ", but I'd like to do something with battery. How about the other faulty? I suppose I should take a ok> prompt with faulty nvram like show above |
|
05-31-2009
|
||||
|
||||
|
try use a SUN keyboard and use Stop+A sequence,
poweroff and replace the NVRAM, type printenv and ensure auto-boot? is false and diag-level is min |
|
06-03-2009
|
||||
|
||||
|
Hi
the message: 0>POST: Return to OBP. SC Alert: Host System has Reset Could not read diag-switch? from NVRAM! shows you error. The ALOM is okay, the POST has run, then the server will return to OBP, therefor he reads the contents of the NVRAM. But your NVRAM is flashed, you can't boot or install Solaris, cause the NVRAM is the BIOS of the V440, where all pathes and infos for your hardware is been saved. The only way is to install a new NVRAM, you need a support contract and a service call, or a new motherboard. cu lowbyte |
|
| Bookmarks |
| Tags |
| fire v440 error cpu boot |
| Thread Tools | Search this Thread |
| Display Modes | Rate This Thread |
|
|
Hybrid Mode
