net(5) [debian man page]

NET(5)								File Formats Manual							    NET(5)

NAME

       net - format of .net files read/written by Magic's netlist editor

DESCRIPTION

       Netlist	files  are  read  and  written	by  Magic's  netlist editor in a very simple ASCII format.  The first line contains the characters
       ``  Netlist File'' (the leading blank is important).  After that comes a blank line and then the descriptions of one or	more  nets.   Each
       net  contains one or more lines, where each line contains a single terminal name.  The nets are separated by blank lines.  Any line that is
       blank or whose first character is blank is considered to be a separator line and the rest of its contents are ignored.

       Each terminal name is a path, much like a file path name in Unix.  It consists of one or more fields separated by slashes.  The last  field
       in the path is the name of a label in a cell.  The other fields (if any), are cell instance identifiers that form a path from the edit cell
       down to the label.  The first instance identifier must name a subcell of the edit cell, the second must be a subcell of the first,  and	so
       on.

       Instance  identifiers  are  unique  within their parent cells, so a terminal path selects a unique cell to contain the label.  However, the
       same label may appear multiple times within its cell.  When this occurs, Magic assumes that  the  identical  labels  identify  electrically
       equivalent  terminals;  it will choose the closest of them when routing to that terminal.  Further, after connecting to one of these termi-
       nals Magic may take advantage of the internal wiring connecting them together and route through a cell to complete the net's wiring.

       An example netlist file follows below.  It contains three distinct nets.

       ----------------------------------------
	       Netlist File

	      alu/bit_1/cout
	      alu/bit_2/cin

	      regcell[21,2]/output
	      latch[2]/input
	       This line starts with a blank, so it's a separator.
	      opcode_pla/out6
	      shifter/drivers/shift2
       ----------------------------------------

SEE ALSO

       magic(1)

4th Berkeley Distribution														    NET(5)

Netlist::Cell(3pm)					User Contributed Perl Documentation					Netlist::Cell(3pm)

NAME

       Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist

SYNOPSIS

	 use Verilog::Netlist;

	 ...
	 my $cell = $module->find_cell ('cellname');
	 print $cell->name;

DESCRIPTION

       A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.

ACCESSORS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->comment
	   Returns any comments following the definition.  keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.

       $self->delete
	   Delete the cell from the module it's under.

       $self->gateprim
	   True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.

       $self->module
	   Pointer to the module the cell is in.

       $self->name
	   The instantiation name of the cell.

       $self->netlist
	   Reference to the Verilog::Netlist the cell is under.

       $self->pins
	   List of Verilog::Netlist::Pin connections for the cell.

       $self->pins_sorted
	   List of name sorted Verilog::Netlist::Pin connections for the cell.

       $self->submod
	   Reference to the Verilog::Netlist::Module the cell instantiates.  Only valid after the design is linked.

       $self->submodname
	   The module name the cell instantiates (under the cell).

MEMBER FUNCTIONS

       See also Verilog::Netlist::Subclass for additional accessors and methods.

       $self->lint
	   Checks the cell for errors.	Normally called by Verilog::Netlist::lint.

       $self->new_pin
	   Creates a new Verilog::Netlist::Pin connection for this cell.

       $self->pins_sorted
	   Returns all Verilog::Netlist::Pin connections for this cell.

       $self->dump
	   Prints debugging information for this cell.

DISTRIBUTION

       Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite.  The latest version is available from CPAN and
       from http://www.veripool.org/verilog-perl <http://www.veripool.org/verilog-perl>.

       Copyright 2000-2012 by Wilson Snyder.  This package is free software; you can redistribute it and/or modify it under the terms of either
       the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

perl v5.14.2							    2012-05-04							Netlist::Cell(3pm)