dpgen_shift(3) [debian man page]

DPGEN_SHIFT(3)						  Alliance - genlib User's Manual					    DPGEN_SHIFT(3)

NAME

       DPGEN_SHIFT - Shifter Macro-Generator

SYNOPSIS

       #include  <genlib.h>

       void GENLIB_MACRO (DPGEN_SHIFT, char *modelname, long flags, long N);

DESCRIPTION

       Generate a N bits shifter with name modelname.

       How it works :

       o if the op[0] signal is set to '1' performs a right shift, performs a left shift otherwise.

       o if the op[1] signal is set to '1' performs an arithmetic shift (only meaningful in case of a right shift).

       o shamt : specifies the shift amount. The width of this signal (Y) is computed from the operator's width : Y = ceil(log2(N)) - 1.

   TERMINAL NAMES
       1. op : select the kind of shift (input, 2 bit).

       2. shamt : the shift amount (input, Y bits).

       3. i : value to shift (input, N bits).

       4. o : output (N bits).

       5. vdd : power.

       6. vss : ground.

EXAMPLE

       GENLIB_MACRO(DPGEN_SHIFT, "model_shift_32",
				 F_BEHAV|F_PLACE,
				 32);

       GENLIB_LOINS("model_shift_32",
		    "instance1_shift_32",
		    "op[1:0]",
		    "shamt[4:0]",
		    "x[31:0]",
		    "y[31:0]",
		    "vdd", "vss", NULL);

SEE ALSO

       GENLIB_MACRO(3), genlib(1)

ASIM
/LIP6							   30 July 2004 						    DPGEN_SHIFT(3)

DPGEN_ADSB2F(3) 					  Alliance - genlib User's Manual					   DPGEN_ADSB2F(3)

NAME

       DPGEN_ADSB2F - Adder/Substractor Macro-Generator

SYNOPSIS

       #include  <genlib.h>

       void GENLIB_MACRO (DPGEN_ADSB2F, char *modelname, long flags, long N);

DESCRIPTION

       Generate a N bits adder/substractor named modelname.

       How it works :

       o if the add_sub signal is set to '0' an addition is performed, otherwise it's a substraction.

       o Operation can be either signed or unsigned. In unsigned mode c31 is the overflow, in unsigned mode you have to compute overflow by XORing
	 c31 and c30.

   TERMINAL NAMES
       1. add_sub : select addition or substraction (input, 1 bit).

       2. c31 : carry out. In unsigned mode, this is the overflow (output, 1 bits).

       3. c30 : used to compute overflow in signed mode : overflow := c31 xor c30 (output, 1 bits).

       4. i1 : first operand (input, N bits).

       5. i0 : second operand (input, N bits).

       6. q : output (N bits).

       7. vdd : power.

       8. vss : ground.

EXAMPLE

       GENLIB_MACRO(DPGEN_ADSB2F, "model_adsb2f_32"
				   , F_BEHAV|F_PLACE
				   , 32
				   );

       GENLIB_LOINS( "model_adsb2f_32"
		   , "instance1_adsb2f_32"
		   , "add_sub"
		   , "c32"
		   , "c31"
		   , "i1[31:0]"
		   , "i0[31:0]"
		   ,  "q[31:0]"
		   , "vdd", "vss", NULL
		   );

SEE ALSO

       GENLIB_MACRO(3), genlib(1)

ASIM
/LIP6							   30 July 2004 						   DPGEN_ADSB2F(3)